multi8x8.tan.qmsg

VHDL实现的8位乘法器

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "REG16B:inst3\|r16s\[2\] REG16B:inst3\|r16s\[1\] clk 429 ps " "Info: Found hold time violation between source  pin or register \"REG16B:inst3\|r16s\[2\]\" and destination pin or register \"REG16B:inst3\|r16s\[1\]\" for clock \"clk\" (Hold time is 429 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.096 ns + Largest " "Info: + Largest clock skew is 1.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.641 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "" { clk } "NODE_NAME" } "" } } { "multi8x8.bdf" "" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 48 24 192 64 "clk" "" } { 40 192 240 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.720 ns) 2.301 ns ARICTL:inst\|cnt4b\[3\] 2 REG LC_X7_Y9_N5 6 " "Info: 2: + IC(0.451 ns) + CELL(0.720 ns) = 2.301 ns; Loc. = LC_X7_Y9_N5; Fanout = 6; REG Node = 'ARICTL:inst\|cnt4b\[3\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "1.171 ns" { clk ARICTL:inst|cnt4b[3] } "NODE_NAME" } "" } } { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.436 ns) + CELL(0.340 ns) 3.077 ns ARICTL:inst\|clkout~24 3 COMB LC_X7_Y9_N7 23 " "Info: 3: + IC(0.436 ns) + CELL(0.340 ns) = 3.077 ns; Loc. = LC_X7_Y9_N7; Fanout = 23; COMB Node = 'ARICTL:inst\|clkout~24'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.776 ns" { ARICTL:inst|cnt4b[3] ARICTL:inst|clkout~24 } "NODE_NAME" } "" } } { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.017 ns) + CELL(0.547 ns) 6.641 ns REG16B:inst3\|r16s\[1\] 4 REG LC_X20_Y1_N9 2 " "Info: 4: + IC(3.017 ns) + CELL(0.547 ns) = 6.641 ns; Loc. = LC_X20_Y1_N9; Fanout = 2; REG Node = 'REG16B:inst3\|r16s\[1\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "3.564 ns" { ARICTL:inst|clkout~24 REG16B:inst3|r16s[1] } "NODE_NAME" } "" } } { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.737 ns ( 41.21 % ) " "Info: Total cell delay = 2.737 ns ( 41.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.904 ns ( 58.79 % ) " "Info: Total interconnect delay = 3.904 ns ( 58.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "6.641 ns" { clk ARICTL:inst|cnt4b[3] ARICTL:inst|clkout~24 REG16B:inst3|r16s[1] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "6.641 ns" { clk clk~out0 ARICTL:inst|cnt4b[3] ARICTL:inst|clkout~24 REG16B:inst3|r16s[1] } { 0.000ns 0.000ns 0.451ns 0.436ns 3.017ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.545 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 5.545 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_10 5 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_10; Fanout = 5; CLK Node = 'clk'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "" { clk } "NODE_NAME" } "" } } { "multi8x8.bdf" "" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 48 24 192 64 "clk" "" } { 40 192 240 56 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.763 ns) + CELL(0.088 ns) 1.981 ns ARICTL:inst\|clkout~24 2 COMB LC_X7_Y9_N7 23 " "Info: 2: + IC(0.763 ns) + CELL(0.088 ns) = 1.981 ns; Loc. = LC_X7_Y9_N7; Fanout = 23; COMB Node = 'ARICTL:inst\|clkout~24'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.851 ns" { clk ARICTL:inst|clkout~24 } "NODE_NAME" } "" } } { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.017 ns) + CELL(0.547 ns) 5.545 ns REG16B:inst3\|r16s\[2\] 3 REG LC_X20_Y1_N4 2 " "Info: 3: + IC(3.017 ns) + CELL(0.547 ns) = 5.545 ns; Loc. = LC_X20_Y1_N4; Fanout = 2; REG Node = 'REG16B:inst3\|r16s\[2\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "3.564 ns" { ARICTL:inst|clkout~24 REG16B:inst3|r16s[2] } "NODE_NAME" } "" } } { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.765 ns ( 31.83 % ) " "Info: Total cell delay = 1.765 ns ( 31.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.780 ns ( 68.17 % ) " "Info: Total interconnect delay = 3.780 ns ( 68.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "5.545 ns" { clk ARICTL:inst|clkout~24 REG16B:inst3|r16s[2] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.545 ns" { clk clk~out0 ARICTL:inst|clkout~24 REG16B:inst3|r16s[2] } { 0.000ns 0.000ns 0.763ns 3.017ns } { 0.000ns 1.130ns 0.088ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "6.641 ns" { clk ARICTL:inst|cnt4b[3] ARICTL:inst|clkout~24 REG16B:inst3|r16s[1] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "6.641 ns" { clk clk~out0 ARICTL:inst|cnt4b[3] ARICTL:inst|clkout~24 REG16B:inst3|r16s[1] } { 0.000ns 0.000ns 0.451ns 0.436ns 3.017ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "5.545 ns" { clk ARICTL:inst|clkout~24 REG16B:inst3|r16s[2] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.545 ns" { clk clk~out0 ARICTL:inst|clkout~24 REG16B:inst3|r16s[2] } { 0.000ns 0.000ns 0.763ns 3.017ns } { 0.000ns 1.130ns 0.088ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" {  } { { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.506 ns - Shortest register register " "Info: - Shortest register to register delay is 0.506 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG16B:inst3\|r16s\[2\] 1 REG LC_X20_Y1_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y1_N4; Fanout = 2; REG Node = 'REG16B:inst3\|r16s\[2\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "" { REG16B:inst3|r16s[2] } "NODE_NAME" } "" } } { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.089 ns) 0.506 ns REG16B:inst3\|r16s\[1\] 2 REG LC_X20_Y1_N9 2 " "Info: 2: + IC(0.417 ns) + CELL(0.089 ns) = 0.506 ns; Loc. = LC_X20_Y1_N9; Fanout = 2; REG Node = 'REG16B:inst3\|r16s\[1\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.506 ns" { REG16B:inst3|r16s[2] REG16B:inst3|r16s[1] } "NODE_NAME" } "" } } { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.089 ns ( 17.59 % ) " "Info: Total cell delay = 0.089 ns ( 17.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.417 ns ( 82.41 % ) " "Info: Total interconnect delay = 0.417 ns ( 82.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.506 ns" { REG16B:inst3|r16s[2] REG16B:inst3|r16s[1] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "0.506 ns" { REG16B:inst3|r16s[2] REG16B:inst3|r16s[1] } { 0.000ns 0.417ns } { 0.000ns 0.089ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "6.641 ns" { clk ARICTL:inst|cnt4b[3] ARICTL:inst|clkout~24 REG16B:inst3|r16s[1] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "6.641 ns" { clk clk~out0 ARICTL:inst|cnt4b[3] ARICTL:inst|clkout~24 REG16B:inst3|r16s[1] } { 0.000ns 0.000ns 0.451ns 0.436ns 3.017ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "5.545 ns" { clk ARICTL:inst|clkout~24 REG16B:inst3|r16s[2] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.545 ns" { clk clk~out0 ARICTL:inst|clkout~24 REG16B:inst3|r16s[2] } { 0.000ns 0.000ns 0.763ns 3.017ns } { 0.000ns 1.130ns 0.088ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.506 ns" { REG16B:inst3|r16s[2] REG16B:inst3|r16s[1] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "0.506 ns" { REG16B:inst3|r16s[2] REG16B:inst3|r16s[1] } { 0.000ns 0.417ns } { 0.000ns 0.089ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "start 1 " "Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock \"start\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "SREG8B:inst1\|reg8\[7\] SREG8B:inst1\|reg8\[6\] start 3.631 ns " "Info: Found hold time violation between source  pin or register \"SREG8B:inst1\|reg8\[7\]\" and destination pin or register \"SREG8B:inst1\|reg8\[6\]\" for clock \"start\" (Hold time is 3.631 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.733 ns + Largest " "Info: + Largest clock skew is 3.733 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start destination 5.812 ns + Longest register " "Info: + Longest clock path from clock \"start\" to destination register is 5.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns start 1 CLK PIN_66 30 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 30; CLK Node = 'start'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "" { start } "NODE_NAME" } "" } } { "multi8x8.bdf" "" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 88 24 192 104 "start" "" } { 80 192 240 96 "start" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.225 ns) 2.248 ns ARICTL:inst\|clkout~24 2 COMB LC_X7_Y9_N7 23 " "Info: 2: + IC(0.893 ns) + CELL(0.225 ns) = 2.248 ns; Loc. = LC_X7_Y9_N7; Fanout = 23; COMB Node = 'ARICTL:inst\|clkout~24'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "1.118 ns" { start ARICTL:inst|clkout~24 } "NODE_NAME" } "" } } { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.017 ns) + CELL(0.547 ns) 5.812 ns SREG8B:inst1\|reg8\[6\] 3 REG LC_X26_Y3_N5 1 " "Info: 3: + IC(3.017 ns) + CELL(0.547 ns) = 5.812 ns; Loc. = LC_X26_Y3_N5; Fanout = 1; REG Node = 'SREG8B:inst1\|reg8\[6\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "3.564 ns" { ARICTL:inst|clkout~24 SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.902 ns ( 32.73 % ) " "Info: Total cell delay = 1.902 ns ( 32.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.910 ns ( 67.27 % ) " "Info: Total interconnect delay = 3.910 ns ( 67.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "5.812 ns" { start ARICTL:inst|clkout~24 SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.812 ns" { start start~out0 ARICTL:inst|clkout~24 SREG8B:inst1|reg8[6] } { 0.000ns 0.000ns 0.893ns 3.017ns } { 0.000ns 1.130ns 0.225ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "start source 2.079 ns - Shortest register " "Info: - Shortest clock path from clock \"start\" to source register is 2.079 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns start 1 CLK PIN_66 30 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_66; Fanout = 30; CLK Node = 'start'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "" { start } "NODE_NAME" } "" } } { "multi8x8.bdf" "" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 88 24 192 104 "start" "" } { 80 192 240 96 "start" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.861 ns) + CELL(0.088 ns) 2.079 ns SREG8B:inst1\|reg8\[7\] 2 REG LC_X26_Y3_N5 1 " "Info: 2: + IC(0.861 ns) + CELL(0.088 ns) = 2.079 ns; Loc. = LC_X26_Y3_N5; Fanout = 1; REG Node = 'SREG8B:inst1\|reg8\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.949 ns" { start SREG8B:inst1|reg8[7] } "NODE_NAME" } "" } } { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.218 ns ( 58.59 % ) " "Info: Total cell delay = 1.218 ns ( 58.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.861 ns ( 41.41 % ) " "Info: Total interconnect delay = 0.861 ns ( 41.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "2.079 ns" { start SREG8B:inst1|reg8[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.079 ns" { start start~out0 SREG8B:inst1|reg8[7] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 1.130ns 0.088ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "5.812 ns" { start ARICTL:inst|clkout~24 SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.812 ns" { start start~out0 ARICTL:inst|clkout~24 SREG8B:inst1|reg8[6] } { 0.000ns 0.000ns 0.893ns 3.017ns } { 0.000ns 1.130ns 0.225ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "2.079 ns" { start SREG8B:inst1|reg8[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.079 ns" { start start~out0 SREG8B:inst1|reg8[7] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 1.130ns 0.088ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns - " "Info: - Micro clock to output delay of source is 0.000 ns" {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.114 ns - Shortest register register " "Info: - Shortest register to register delay is 0.114 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SREG8B:inst1\|reg8\[7\] 1 REG LC_X26_Y3_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y3_N5; Fanout = 1; REG Node = 'SREG8B:inst1\|reg8\[7\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "" { SREG8B:inst1|reg8[7] } "NODE_NAME" } "" } } { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.114 ns) 0.114 ns SREG8B:inst1\|reg8\[6\] 2 REG LC_X26_Y3_N5 1 " "Info: 2: + IC(0.000 ns) + CELL(0.114 ns) = 0.114 ns; Loc. = LC_X26_Y3_N5; Fanout = 1; REG Node = 'SREG8B:inst1\|reg8\[6\]'" {  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.114 ns" { SREG8B:inst1|reg8[7] SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.114 ns ( 100.00 % ) " "Info: Total cell delay = 0.114 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.114 ns" { SREG8B:inst1|reg8[7] SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "0.114 ns" { SREG8B:inst1|reg8[7] SREG8B:inst1|reg8[6] } { 0.000ns 0.000ns } { 0.000ns 0.114ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 51 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 49 -1 0 } } { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 51 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "5.812 ns" { start ARICTL:inst|clkout~24 SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "5.812 ns" { start start~out0 ARICTL:inst|clkout~24 SREG8B:inst1|reg8[6] } { 0.000ns 0.000ns 0.893ns 3.017ns } { 0.000ns 1.130ns 0.225ns 0.547ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "2.079 ns" { start SREG8B:inst1|reg8[7] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "2.079 ns" { start start~out0 SREG8B:inst1|reg8[7] } { 0.000ns 0.000ns 0.861ns } { 0.000ns 1.130ns 0.088ns } } } { "d:/altera/bin/Report_Window_01.qrpt" "" { Report "d:/altera/bin/Report_Window_01.qrpt" "Compiler" "multi8x8" "UNKNOWN" "V1" "E:/study/multi8x8/db/multi8x8.quartus_db" { Floorplan "E:/study/multi8x8/" "" "0.114 ns" { SREG8B:inst1|reg8[7] SREG8B:inst1|reg8[6] } "NODE_NAME" } "" } } { "d:/altera/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/bin/Technology_Viewer.qrui" "0.114 ns" { SREG8B:inst1|reg8[7] SREG8B:inst1|reg8[6] } { 0.000ns 0.000ns } { 0.000ns 0.114ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}