multi8x8.tan.qmsg

VHDL实现的8位乘法器

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "SREG8B:inst1\|reg8\[7\] " "Warning: Node \"SREG8B:inst1\|reg8\[7\]\" is a latch" {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 49 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "multi8x8.bdf" "" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 48 24 192 64 "clk" "" } { 40 192 240 56 "clk" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "start " "Info: Assuming node \"start\" is an undefined clock" {  } { { "multi8x8.bdf" "" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 88 24 192 104 "start" "" } { 80 192 240 96 "start" "" } } } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "start" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "ARICTL:inst\|clkout~24 " "Info: Detected gated clock \"ARICTL:inst\|clkout~24\" as buffer" {  } { { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 36 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "ARICTL:inst\|clkout~24" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ARICTL:inst\|cnt4b\[3\] " "Info: Detected ripple clock \"ARICTL:inst\|cnt4b\[3\]\" as buffer" {  } { { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 54 -1 0 } } { "d:/altera/bin/Assignment Editor.qase" "" { Assignment "d:/altera/bin/Assignment Editor.qase" 1 { { 0 "ARICTL:inst\|cnt4b\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}