multi8x8.map.qmsg

VHDL实现的8位乘法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition " "Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 29 12:10:03 2008 " "Info: Processing started: Sat Mar 29 12:10:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off multi8x8 -c multi8x8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multi8x8 -c multi8x8" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "multi8x8.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file multi8x8.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 multi8x8 " "Info: Found entity 1: multi8x8" {  } { { "multi8x8.bdf" "" { Schematic "E:/study/multi8x8/multi8x8.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ARICTL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ARICTL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ARICTL-ARICTL_architecture " "Info: Found design unit 1: ARICTL-ARICTL_architecture" {  } { { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 46 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ARICTL " "Info: Found entity 1: ARICTL" {  } { { "ARICTL.vhd" "" { Text "E:/study/multi8x8/ARICTL.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SREG8B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SREG8B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SREG8B-SREG8B_architecture " "Info: Found design unit 1: SREG8B-SREG8B_architecture" {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SREG8B " "Info: Found entity 1: SREG8B" {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ANDARITH.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ANDARITH.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ANDARITH-ANDARITH_architecture " "Info: Found design unit 1: ANDARITH-ANDARITH_architecture" {  } { { "ANDARITH.vhd" "" { Text "E:/study/multi8x8/ANDARITH.vhd" 44 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ANDARITH " "Info: Found entity 1: ANDARITH" {  } { { "ANDARITH.vhd" "" { Text "E:/study/multi8x8/ANDARITH.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER8B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER8B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER8B-bdf_type " "Info: Found design unit 1: ADDER8B-bdf_type" {  } { { "ADDER8B.vhd" "" { Text "E:/study/multi8x8/ADDER8B.vhd" 34 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER8B " "Info: Found entity 1: ADDER8B" {  } { { "ADDER8B.vhd" "" { Text "E:/study/multi8x8/ADDER8B.vhd" 23 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG16B.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG16B.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG16B-REG16B_architecture " "Info: Found design unit 1: REG16B-REG16B_architecture" {  } { { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 REG16B " "Info: Found entity 1: REG16B" {  } { { "REG16B.vhd" "" { Text "E:/study/multi8x8/REG16B.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "multi8x8 " "Info: Elaborating entity \"multi8x8\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ARICTL ARICTL:inst " "Info: Elaborating entity \"ARICTL\" for hierarchy \"ARICTL:inst\"" {  } { { "multi8x8.bdf" "inst" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 32 240 360 128 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG16B REG16B:inst3 " "Info: Elaborating entity \"REG16B\" for hierarchy \"REG16B:inst3\"" {  } { { "multi8x8.bdf" "inst3" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 296 480 600 408 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER8B ADDER8B:inst2 " "Info: Elaborating entity \"ADDER8B\" for hierarchy \"ADDER8B:inst2\"" {  } { { "multi8x8.bdf" "inst2" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 120 616 744 224 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "add4b.vhd 2 1 " "Warning: Using design file add4b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 add4b-add4b_architecture " "Info: Found design unit 1: add4b-add4b_architecture" {  } { { "add4b.vhd" "" { Text "E:/study/multi8x8/add4b.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 add4b " "Info: Found entity 1: add4b" {  } { { "add4b.vhd" "" { Text "E:/study/multi8x8/add4b.vhd" 28 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add4b ADDER8B:inst2\|add4b:b2v_inst " "Info: Elaborating entity \"add4b\" for hierarchy \"ADDER8B:inst2\|add4b:b2v_inst\"" {  } { { "ADDER8B.vhd" "b2v_inst" { Text "E:/study/multi8x8/ADDER8B.vhd" 53 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ANDARITH ANDARITH:inst4 " "Info: Elaborating entity \"ANDARITH\" for hierarchy \"ANDARITH:inst4\"" {  } { { "multi8x8.bdf" "inst4" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 384 160 304 472 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SREG8B SREG8B:inst1 " "Info: Elaborating entity \"SREG8B\" for hierarchy \"SREG8B:inst1\"" {  } { { "multi8x8.bdf" "inst1" { Schematic "E:/study/multi8x8/multi8x8.bdf" { { 200 176 296 304 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "din SREG8B.vhd(52) " "Warning (10492): VHDL Process Statement warning at SREG8B.vhd(52): signal \"din\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 52 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "reg8 SREG8B.vhd(49) " "Warning (10631): VHDL Process Statement warning at SREG8B.vhd(49): signal or variable \"reg8\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"reg8\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "SREG8B.vhd" "" { Text "E:/study/multi8x8/SREG8B.vhd" 49 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "73 " "Info: Implemented 73 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "38 " "Info: Implemented 38 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 29 12:10:04 2008 " "Info: Processing ended: Sat Mar 29 12:10:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}