multi8x8.fit.eqn

VHDL实现的8位乘法器

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--B1_cnt4b[3] is ARICTL:inst|cnt4b[3] at LC_X7_Y9_N5
--operation mode is normal

B1_cnt4b[3]_lut_out = B1_cnt4b[3] # B1_cnt4b[2] & B1_cnt4b[1] & B1_cnt4b[0];
B1_cnt4b[3] = DFFEAS(B1_cnt4b[3]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );


--B1L1 is ARICTL:inst|ariend~9 at LC_X7_Y9_N8
--operation mode is normal

B1L1 = !start & B1_cnt4b[3];


--E1_r16s[15] is REG16B:inst3|r16s[15] at LC_X20_Y13_N8
--operation mode is normal

E1_r16s[15]_carry_eqn = (!E1L22 & E1L32) # (E1L22 & E1L33);
E1_r16s[15]_lut_out = !E1_r16s[15]_carry_eqn;
E1_r16s[15] = DFFEAS(E1_r16s[15]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );


--E1_r16s[14] is REG16B:inst3|r16s[14] at LC_X20_Y13_N7
--operation mode is arithmetic

E1_r16s[14]_carry_eqn = (!E1L22 & E1L29) # (E1L22 & E1L30);
E1_r16s[14]_lut_out = F1_dout[7] $ E1_r16s[15] $ E1_r16s[14]_carry_eqn;
E1_r16s[14] = DFFEAS(E1_r16s[14]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L32 is REG16B:inst3|r16s[14]~82 at LC_X20_Y13_N7
--operation mode is arithmetic

E1L32_cout_0 = F1_dout[7] & !E1_r16s[15] & !E1L29 # !F1_dout[7] & (!E1L29 # !E1_r16s[15]);
E1L32 = CARRY(E1L32_cout_0);

--E1L33 is REG16B:inst3|r16s[14]~82COUT1_126 at LC_X20_Y13_N7
--operation mode is arithmetic

E1L33_cout_1 = F1_dout[7] & !E1_r16s[15] & !E1L30 # !F1_dout[7] & (!E1L30 # !E1_r16s[15]);
E1L33 = CARRY(E1L33_cout_1);


--E1_r16s[13] is REG16B:inst3|r16s[13] at LC_X20_Y13_N6
--operation mode is arithmetic

E1_r16s[13]_carry_eqn = (!E1L22 & E1L26) # (E1L22 & E1L27);
E1_r16s[13]_lut_out = E1_r16s[14] $ F1_dout[6] $ !E1_r16s[13]_carry_eqn;
E1_r16s[13] = DFFEAS(E1_r16s[13]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L29 is REG16B:inst3|r16s[13]~86 at LC_X20_Y13_N6
--operation mode is arithmetic

E1L29_cout_0 = E1_r16s[14] & (F1_dout[6] # !E1L26) # !E1_r16s[14] & F1_dout[6] & !E1L26;
E1L29 = CARRY(E1L29_cout_0);

--E1L30 is REG16B:inst3|r16s[13]~86COUT1_125 at LC_X20_Y13_N6
--operation mode is arithmetic

E1L30_cout_1 = E1_r16s[14] & (F1_dout[6] # !E1L27) # !E1_r16s[14] & F1_dout[6] & !E1L27;
E1L30 = CARRY(E1L30_cout_1);


--E1_r16s[12] is REG16B:inst3|r16s[12] at LC_X20_Y13_N5
--operation mode is arithmetic

E1_r16s[12]_carry_eqn = (!E1L22 & GND) # (E1L22 & VCC);
E1_r16s[12]_lut_out = E1_r16s[13] $ F1_dout[5] $ E1_r16s[12]_carry_eqn;
E1_r16s[12] = DFFEAS(E1_r16s[12]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L26 is REG16B:inst3|r16s[12]~90 at LC_X20_Y13_N5
--operation mode is arithmetic

E1L26_cout_0 = E1_r16s[13] & !F1_dout[5] & !E1L22 # !E1_r16s[13] & (!E1L22 # !F1_dout[5]);
E1L26 = CARRY(E1L26_cout_0);

--E1L27 is REG16B:inst3|r16s[12]~90COUT1_124 at LC_X20_Y13_N5
--operation mode is arithmetic

E1L27_cout_1 = E1_r16s[13] & !F1_dout[5] & !E1L22 # !E1_r16s[13] & (!E1L22 # !F1_dout[5]);
E1L27 = CARRY(E1L27_cout_1);


--E1_r16s[11] is REG16B:inst3|r16s[11] at LC_X20_Y13_N4
--operation mode is arithmetic

E1_r16s[11]_lut_out = F1_dout[4] $ E1_r16s[12] $ !E1L19;
E1_r16s[11] = DFFEAS(E1_r16s[11]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L22 is REG16B:inst3|r16s[11]~94 at LC_X20_Y13_N4
--operation mode is arithmetic

E1L22 = E1L23;


--E1_r16s[10] is REG16B:inst3|r16s[10] at LC_X20_Y13_N3
--operation mode is arithmetic

E1_r16s[10]_lut_out = F1_dout[3] $ E1_r16s[11] $ E1L16;
E1_r16s[10] = DFFEAS(E1_r16s[10]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L19 is REG16B:inst3|r16s[10]~98 at LC_X20_Y13_N3
--operation mode is arithmetic

E1L19_cout_0 = F1_dout[3] & !E1_r16s[11] & !E1L16 # !F1_dout[3] & (!E1L16 # !E1_r16s[11]);
E1L19 = CARRY(E1L19_cout_0);

--E1L20 is REG16B:inst3|r16s[10]~98COUT1 at LC_X20_Y13_N3
--operation mode is arithmetic

E1L20_cout_1 = F1_dout[3] & !E1_r16s[11] & !E1L17 # !F1_dout[3] & (!E1L17 # !E1_r16s[11]);
E1L20 = CARRY(E1L20_cout_1);


--E1_r16s[9] is REG16B:inst3|r16s[9] at LC_X20_Y13_N2
--operation mode is arithmetic

E1_r16s[9]_lut_out = F1_dout[2] $ E1_r16s[10] $ !E1L13;
E1_r16s[9] = DFFEAS(E1_r16s[9]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L16 is REG16B:inst3|r16s[9]~102 at LC_X20_Y13_N2
--operation mode is arithmetic

E1L16_cout_0 = F1_dout[2] & (E1_r16s[10] # !E1L13) # !F1_dout[2] & E1_r16s[10] & !E1L13;
E1L16 = CARRY(E1L16_cout_0);

--E1L17 is REG16B:inst3|r16s[9]~102COUT1_123 at LC_X20_Y13_N2
--operation mode is arithmetic

E1L17_cout_1 = F1_dout[2] & (E1_r16s[10] # !E1L14) # !F1_dout[2] & E1_r16s[10] & !E1L14;
E1L17 = CARRY(E1L17_cout_1);


--E1_r16s[8] is REG16B:inst3|r16s[8] at LC_X20_Y13_N1
--operation mode is arithmetic

E1_r16s[8]_lut_out = E1_r16s[9] $ F1_dout[1] $ E1L10;
E1_r16s[8] = DFFEAS(E1_r16s[8]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L13 is REG16B:inst3|r16s[8]~106 at LC_X20_Y13_N1
--operation mode is arithmetic

E1L13_cout_0 = E1_r16s[9] & !F1_dout[1] & !E1L10 # !E1_r16s[9] & (!E1L10 # !F1_dout[1]);
E1L13 = CARRY(E1L13_cout_0);

--E1L14 is REG16B:inst3|r16s[8]~106COUT1_122 at LC_X20_Y13_N1
--operation mode is arithmetic

E1L14_cout_1 = E1_r16s[9] & !F1_dout[1] & !E1L11 # !E1_r16s[9] & (!E1L11 # !F1_dout[1]);
E1L14 = CARRY(E1L14_cout_1);


--E1_r16s[7] is REG16B:inst3|r16s[7] at LC_X20_Y13_N0
--operation mode is arithmetic

E1_r16s[7]_lut_out = F1_dout[0] $ E1_r16s[8];
E1_r16s[7] = DFFEAS(E1_r16s[7]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );

--E1L10 is REG16B:inst3|r16s[7]~110 at LC_X20_Y13_N0
--operation mode is arithmetic

E1L10_cout_0 = F1_dout[0] & E1_r16s[8];
E1L10 = CARRY(E1L10_cout_0);

--E1L11 is REG16B:inst3|r16s[7]~110COUT1_121 at LC_X20_Y13_N0
--operation mode is arithmetic

E1L11_cout_1 = F1_dout[0] & E1_r16s[8];
E1L11 = CARRY(E1L11_cout_1);


--E1_r16s[6] is REG16B:inst3|r16s[6] at LC_X20_Y1_N5
--operation mode is normal

E1_r16s[6]_lut_out = E1_r16s[7];
E1_r16s[6] = DFFEAS(E1_r16s[6]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );


--E1_r16s[5] is REG16B:inst3|r16s[5] at LC_X20_Y1_N7
--operation mode is normal

E1_r16s[5]_lut_out = E1_r16s[6];
E1_r16s[5] = DFFEAS(E1_r16s[5]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , , , , );


--E1_r16s[4] is REG16B:inst3|r16s[4] at LC_X20_Y1_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_r16s[4]_lut_out = GND;
E1_r16s[4] = DFFEAS(E1_r16s[4]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , E1_r16s[5], , , VCC);


--E1_r16s[3] is REG16B:inst3|r16s[3] at LC_X20_Y1_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_r16s[3]_lut_out = GND;
E1_r16s[3] = DFFEAS(E1_r16s[3]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , E1_r16s[4], , , VCC);


--E1_r16s[2] is REG16B:inst3|r16s[2] at LC_X20_Y1_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_r16s[2]_lut_out = GND;
E1_r16s[2] = DFFEAS(E1_r16s[2]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , E1_r16s[3], , , VCC);


--E1_r16s[1] is REG16B:inst3|r16s[1] at LC_X20_Y1_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_r16s[1]_lut_out = GND;
E1_r16s[1] = DFFEAS(E1_r16s[1]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , E1_r16s[2], , , VCC);


--E1_r16s[0] is REG16B:inst3|r16s[0] at LC_X20_Y1_N6
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

E1_r16s[0]_lut_out = GND;
E1_r16s[0] = DFFEAS(E1_r16s[0]_lut_out, GLOBAL(B1L2), !GLOBAL(start), , , E1_r16s[1], , , VCC);


--B1_cnt4b[2] is ARICTL:inst|cnt4b[2] at LC_X7_Y9_N6
--operation mode is normal

B1_cnt4b[2]_lut_out = B1_cnt4b[2] $ (!B1_cnt4b[3] & B1_cnt4b[1] & B1_cnt4b[0]);
B1_cnt4b[2] = DFFEAS(B1_cnt4b[2]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );


--B1_cnt4b[1] is ARICTL:inst|cnt4b[1] at LC_X7_Y9_N2
--operation mode is normal

B1_cnt4b[1]_lut_out = B1_cnt4b[1] $ (B1_cnt4b[0] & !B1_cnt4b[3]);
B1_cnt4b[1] = DFFEAS(B1_cnt4b[1]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );


--B1_cnt4b[0] is ARICTL:inst|cnt4b[0] at LC_X7_Y9_N9
--operation mode is normal

B1_cnt4b[0]_lut_out = B1_cnt4b[3] $ !B1_cnt4b[0];
B1_cnt4b[0] = DFFEAS(B1_cnt4b[0]_lut_out, GLOBAL(clk), !GLOBAL(start), , , , , , );


--B1L2 is ARICTL:inst|clkout~24 at LC_X7_Y9_N7
--operation mode is normal

B1L2 = !B1_cnt4b[3] & !start & clk;


--C1_reg8[0] is SREG8B:inst1|reg8[0] at LC_X21_Y13_N1
--operation mode is normal

C1_reg8[0]_lut_out = C1_reg8[1];
C1_reg8[0] = DFFEAS(C1_reg8[0]_lut_out, GLOBAL(B1L2), VCC, , , a[0], GLOBAL(start), , );


--F1_dout[7] is ANDARITH:inst4|dout[7] at LC_X21_Y13_N7
--operation mode is normal

F1_dout[7] = b[7] & (C1_reg8[0]);


--F1_dout[6] is ANDARITH:inst4|dout[6] at LC_X21_Y13_N5
--operation mode is normal

F1_dout[6] = b[6] & C1_reg8[0];


--F1_dout[5] is ANDARITH:inst4|dout[5] at LC_X21_Y13_N0
--operation mode is normal

F1_dout[5] = b[5] & (C1_reg8[0]);


--F1_dout[4] is ANDARITH:inst4|dout[4] at LC_X21_Y13_N2
--operation mode is normal

F1_dout[4] = b[4] & (C1_reg8[0]);


--F1_dout[3] is ANDARITH:inst4|dout[3] at LC_X21_Y13_N8
--operation mode is normal

F1_dout[3] = b[3] & C1_reg8[0];


--F1_dout[2] is ANDARITH:inst4|dout[2] at LC_X21_Y13_N9
--operation mode is normal

F1_dout[2] = b[2] & (C1_reg8[0]);


--F1_dout[1] is ANDARITH:inst4|dout[1] at LC_X21_Y13_N4
--operation mode is normal

F1_dout[1] = b[1] & C1_reg8[0];


--F1_dout[0] is ANDARITH:inst4|dout[0] at LC_X20_Y13_N9
--operation mode is normal

F1_dout[0] = b[0] & (C1_reg8[0]);


--C1_reg8[1] is SREG8B:inst1|reg8[1] at LC_X21_Y13_N6
--operation mode is normal

C1_reg8[1]_lut_out = C1_reg8[2];
C1_reg8[1] = DFFEAS(C1_reg8[1]_lut_out, GLOBAL(B1L2), VCC, , , a[1], GLOBAL(start), , );


--C1_reg8[2] is SREG8B:inst1|reg8[2] at LC_X21_Y13_N3
--operation mode is normal

C1_reg8[2]_lut_out = C1_reg8[3];
C1_reg8[2] = DFFEAS(C1_reg8[2]_lut_out, GLOBAL(B1L2), VCC, , , a[2], GLOBAL(start), , );


--C1_reg8[3] is SREG8B:inst1|reg8[3] at LC_X26_Y3_N2
--operation mode is normal

C1_reg8[3]_lut_out = C1_reg8[4];
C1_reg8[3] = DFFEAS(C1_reg8[3]_lut_out, GLOBAL(B1L2), VCC, , , a[3], GLOBAL(start), , );


--C1_reg8[4] is SREG8B:inst1|reg8[4] at LC_X26_Y3_N6
--operation mode is normal

C1_reg8[4]_lut_out = C1_reg8[5];
C1_reg8[4] = DFFEAS(C1_reg8[4]_lut_out, GLOBAL(B1L2), VCC, , , a[4], GLOBAL(start), , );


--C1_reg8[5] is SREG8B:inst1|reg8[5] at LC_X26_Y3_N4
--operation mode is normal

C1_reg8[5]_lut_out = C1_reg8[6];
C1_reg8[5] = DFFEAS(C1_reg8[5]_lut_out, GLOBAL(B1L2), VCC, , , a[5], GLOBAL(start), , );


--C1_reg8[7] is SREG8B:inst1|reg8[7] at LC_X26_Y3_N5
--operation mode is normal

C1_reg8[7] = GLOBAL(start) & (a[7]) # !GLOBAL(start) & C1_reg8[7];

--C1_reg8[6] is SREG8B:inst1|reg8[6] at LC_X26_Y3_N5
--operation mode is normal

C1_reg8[6] = DFFEAS(C1_reg8[7], GLOBAL(B1L2), VCC, , , a[6], GLOBAL(start), , );


--start is start at PIN_66
--operation mode is input

start = INPUT();


--clk is clk at PIN_10
--operation mode is input

clk = INPUT();


--b[7] is b[7] at PIN_70
--operation mode is input

b[7] = INPUT();


--b[6] is b[6] at PIN_71
--operation mode is input

b[6] = INPUT();


--b[5] is b[5] at PIN_74
--operation mode is input

b[5] = INPUT();


--b[4] is b[4] at PIN_78
--operation mode is input

b[4] = INPUT();


--b[3] is b[3] at PIN_72
--operation mode is input

b[3] = INPUT();


--b[2] is b[2] at PIN_89
--operation mode is input

b[2] = INPUT();


--b[1] is b[1] at PIN_84
--operation mode is input

b[1] = INPUT();


--b[0] is b[0] at PIN_87
--operation mode is input

b[0] = INPUT();


--a[0] is a[0] at PIN_54
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_79
--operation mode is input

a[1] = INPUT();


--a[2] is a[2] at PIN_39
--operation mode is input

a[2] = INPUT();


--a[3] is a[3] at PIN_56
--operation mode is input

a[3] = INPUT();


--a[4] is a[4] at PIN_55
--operation mode is input

a[4] = INPUT();


--a[5] is a[5] at PIN_49
--operation mode is input

a[5] = INPUT();


--a[6] is a[6] at PIN_57
--operation mode is input

a[6] = INPUT();


--a[7] is a[7] at PIN_76
--operation mode is input

a[7] = INPUT();


--ariend is ariend at PIN_98
--operation mode is output

ariend = OUTPUT(B1L1);


--dtout[15] is dtout[15] at PIN_90
--operation mode is output

dtout[15] = OUTPUT(E1_r16s[15]);


--dtout[14] is dtout[14] at PIN_73
--operation mode is output

dtout[14] = OUTPUT(E1_r16s[14]);


--dtout[13] is dtout[13] at PIN_75
--operation mode is output

dtout[13] = OUTPUT(E1_r16s[13]);


--dtout[12] is dtout[12] at PIN_88
--operation mode is output

dtout[12] = OUTPUT(E1_r16s[12]);


--dtout[11] is dtout[11] at PIN_1
--operation mode is output

dtout[11] = OUTPUT(E1_r16s[11]);


--dtout[10] is dtout[10] at PIN_85
--operation mode is output

dtout[10] = OUTPUT(E1_r16s[10]);


--dtout[9] is dtout[9] at PIN_2
--operation mode is output

dtout[9] = OUTPUT(E1_r16s[9]);


--dtout[8] is dtout[8] at PIN_86
--operation mode is output

dtout[8] = OUTPUT(E1_r16s[8]);


--dtout[7] is dtout[7] at PIN_53
--operation mode is output

dtout[7] = OUTPUT(E1_r16s[7]);


--dtout[6] is dtout[6] at PIN_41
--operation mode is output

dtout[6] = OUTPUT(E1_r16s[6]);


--dtout[5] is dtout[5] at PIN_51
--operation mode is output

dtout[5] = OUTPUT(E1_r16s[5]);


--dtout[4] is dtout[4] at PIN_40
--operation mode is output

dtout[4] = OUTPUT(E1_r16s[4]);


--dtout[3] is dtout[3] at PIN_42
--operation mode is output

dtout[3] = OUTPUT(E1_r16s[3]);


--dtout[2] is dtout[2] at PIN_48
--operation mode is output

dtout[2] = OUTPUT(E1_r16s[2]);


--dtout[1] is dtout[1] at PIN_47
--operation mode is output

dtout[1] = OUTPUT(E1_r16s[1]);


--dtout[0] is dtout[0] at PIN_38
--operation mode is output

dtout[0] = OUTPUT(E1_r16s[0]);