arictl.vhd

VHDL实现的8位乘法器

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.1 (Build Build 213 01/19/2006)
-- Created on Sat Mar 29 10:35:31 2008

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--  Entity Declaration

ENTITY ARICTL IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk : IN STD_LOGIC;
		start : IN STD_LOGIC;
		ariend : OUT STD_LOGIC;
		clkout : OUT STD_LOGIC;
		rstall : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END ARICTL;


--  Architecture Body

ARCHITECTURE ARICTL_architecture OF ARICTL IS
signal cnt4b: std_logic_vector(3 downto 0);
	
BEGIN
  rstall<=start;

 process(clk,start)
   begin
    if start='1' then
       cnt4b<="0000";
    elsif rising_edge(clk) then
       if cnt4b<8 then
          cnt4b<=cnt4b+1;
       end if;
    end if;
 end process;

 process(clk,cnt4b,start)
   begin
    if start='0' then
      if cnt4b<8 then
        clkout<=clk;
        ariend<='0';
      else
        clkout<='0';
        ariend<='1';
      end if;
    else 
      clkout<='0';
      ariend<='0';
    end if;
 end process;
END ARICTL_architecture;