multi8x8.map.eqn

VHDL实现的8位乘法器

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--B1_cnt4b[3] is ARICTL:inst|cnt4b[3]
--operation mode is normal

B1_cnt4b[3]_lut_out = B1_cnt4b[3] # B1_cnt4b[2] & B1_cnt4b[1] & B1_cnt4b[0];
B1_cnt4b[3] = DFFEAS(B1_cnt4b[3]_lut_out, clk, !start, , , , , , );


--B1L1 is ARICTL:inst|ariend~9
--operation mode is normal

B1L1 = B1_cnt4b[3] & (!start);


--E1_r16s[15] is REG16B:inst3|r16s[15]
--operation mode is normal

E1_r16s[15]_carry_eqn = E1L24;
E1_r16s[15]_lut_out = !E1_r16s[15]_carry_eqn;
E1_r16s[15] = DFFEAS(E1_r16s[15]_lut_out, B1L2, !start, , , , , , );


--E1_r16s[14] is REG16B:inst3|r16s[14]
--operation mode is arithmetic

E1_r16s[14]_carry_eqn = E1L22;
E1_r16s[14]_lut_out = F1_dout[7] $ E1_r16s[15] $ E1_r16s[14]_carry_eqn;
E1_r16s[14] = DFFEAS(E1_r16s[14]_lut_out, B1L2, !start, , , , , , );

--E1L24 is REG16B:inst3|r16s[14]~82
--operation mode is arithmetic

E1L24 = CARRY(F1_dout[7] & !E1_r16s[15] & !E1L22 # !F1_dout[7] & (!E1L22 # !E1_r16s[15]));


--E1_r16s[13] is REG16B:inst3|r16s[13]
--operation mode is arithmetic

E1_r16s[13]_carry_eqn = E1L20;
E1_r16s[13]_lut_out = F1_dout[6] $ E1_r16s[14] $ !E1_r16s[13]_carry_eqn;
E1_r16s[13] = DFFEAS(E1_r16s[13]_lut_out, B1L2, !start, , , , , , );

--E1L22 is REG16B:inst3|r16s[13]~86
--operation mode is arithmetic

E1L22 = CARRY(F1_dout[6] & (E1_r16s[14] # !E1L20) # !F1_dout[6] & E1_r16s[14] & !E1L20);


--E1_r16s[12] is REG16B:inst3|r16s[12]
--operation mode is arithmetic

E1_r16s[12]_carry_eqn = E1L18;
E1_r16s[12]_lut_out = F1_dout[5] $ E1_r16s[13] $ E1_r16s[12]_carry_eqn;
E1_r16s[12] = DFFEAS(E1_r16s[12]_lut_out, B1L2, !start, , , , , , );

--E1L20 is REG16B:inst3|r16s[12]~90
--operation mode is arithmetic

E1L20 = CARRY(F1_dout[5] & !E1_r16s[13] & !E1L18 # !F1_dout[5] & (!E1L18 # !E1_r16s[13]));


--E1_r16s[11] is REG16B:inst3|r16s[11]
--operation mode is arithmetic

E1_r16s[11]_carry_eqn = E1L16;
E1_r16s[11]_lut_out = F1_dout[4] $ E1_r16s[12] $ !E1_r16s[11]_carry_eqn;
E1_r16s[11] = DFFEAS(E1_r16s[11]_lut_out, B1L2, !start, , , , , , );

--E1L18 is REG16B:inst3|r16s[11]~94
--operation mode is arithmetic

E1L18 = CARRY(F1_dout[4] & (E1_r16s[12] # !E1L16) # !F1_dout[4] & E1_r16s[12] & !E1L16);


--E1_r16s[10] is REG16B:inst3|r16s[10]
--operation mode is arithmetic

E1_r16s[10]_carry_eqn = E1L14;
E1_r16s[10]_lut_out = F1_dout[3] $ E1_r16s[11] $ E1_r16s[10]_carry_eqn;
E1_r16s[10] = DFFEAS(E1_r16s[10]_lut_out, B1L2, !start, , , , , , );

--E1L16 is REG16B:inst3|r16s[10]~98
--operation mode is arithmetic

E1L16 = CARRY(F1_dout[3] & !E1_r16s[11] & !E1L14 # !F1_dout[3] & (!E1L14 # !E1_r16s[11]));


--E1_r16s[9] is REG16B:inst3|r16s[9]
--operation mode is arithmetic

E1_r16s[9]_carry_eqn = E1L12;
E1_r16s[9]_lut_out = F1_dout[2] $ E1_r16s[10] $ !E1_r16s[9]_carry_eqn;
E1_r16s[9] = DFFEAS(E1_r16s[9]_lut_out, B1L2, !start, , , , , , );

--E1L14 is REG16B:inst3|r16s[9]~102
--operation mode is arithmetic

E1L14 = CARRY(F1_dout[2] & (E1_r16s[10] # !E1L12) # !F1_dout[2] & E1_r16s[10] & !E1L12);


--E1_r16s[8] is REG16B:inst3|r16s[8]
--operation mode is arithmetic

E1_r16s[8]_carry_eqn = E1L10;
E1_r16s[8]_lut_out = F1_dout[1] $ E1_r16s[9] $ E1_r16s[8]_carry_eqn;
E1_r16s[8] = DFFEAS(E1_r16s[8]_lut_out, B1L2, !start, , , , , , );

--E1L12 is REG16B:inst3|r16s[8]~106
--operation mode is arithmetic

E1L12 = CARRY(F1_dout[1] & !E1_r16s[9] & !E1L10 # !F1_dout[1] & (!E1L10 # !E1_r16s[9]));


--E1_r16s[7] is REG16B:inst3|r16s[7]
--operation mode is arithmetic

E1_r16s[7]_lut_out = F1_dout[0] $ E1_r16s[8];
E1_r16s[7] = DFFEAS(E1_r16s[7]_lut_out, B1L2, !start, , , , , , );

--E1L10 is REG16B:inst3|r16s[7]~110
--operation mode is arithmetic

E1L10 = CARRY(F1_dout[0] & E1_r16s[8]);


--E1_r16s[6] is REG16B:inst3|r16s[6]
--operation mode is normal

E1_r16s[6]_lut_out = E1_r16s[7];
E1_r16s[6] = DFFEAS(E1_r16s[6]_lut_out, B1L2, !start, , , , , , );


--E1_r16s[5] is REG16B:inst3|r16s[5]
--operation mode is normal

E1_r16s[5]_lut_out = E1_r16s[6];
E1_r16s[5] = DFFEAS(E1_r16s[5]_lut_out, B1L2, !start, , , , , , );


--E1_r16s[4] is REG16B:inst3|r16s[4]
--operation mode is normal

E1_r16s[4]_lut_out = E1_r16s[5];
E1_r16s[4] = DFFEAS(E1_r16s[4]_lut_out, B1L2, !start, , , , , , );


--E1_r16s[3] is REG16B:inst3|r16s[3]
--operation mode is normal

E1_r16s[3]_lut_out = E1_r16s[4];
E1_r16s[3] = DFFEAS(E1_r16s[3]_lut_out, B1L2, !start, , , , , , );


--E1_r16s[2] is REG16B:inst3|r16s[2]
--operation mode is normal

E1_r16s[2]_lut_out = E1_r16s[3];
E1_r16s[2] = DFFEAS(E1_r16s[2]_lut_out, B1L2, !start, , , , , , );


--E1_r16s[1] is REG16B:inst3|r16s[1]
--operation mode is normal

E1_r16s[1]_lut_out = E1_r16s[2];
E1_r16s[1] = DFFEAS(E1_r16s[1]_lut_out, B1L2, !start, , , , , , );


--E1_r16s[0] is REG16B:inst3|r16s[0]
--operation mode is normal

E1_r16s[0]_lut_out = E1_r16s[1];
E1_r16s[0] = DFFEAS(E1_r16s[0]_lut_out, B1L2, !start, , , , , , );


--B1_cnt4b[2] is ARICTL:inst|cnt4b[2]
--operation mode is normal

B1_cnt4b[2]_lut_out = B1_cnt4b[2] $ (!B1_cnt4b[3] & B1_cnt4b[1] & B1_cnt4b[0]);
B1_cnt4b[2] = DFFEAS(B1_cnt4b[2]_lut_out, clk, !start, , , , , , );


--B1_cnt4b[1] is ARICTL:inst|cnt4b[1]
--operation mode is normal

B1_cnt4b[1]_lut_out = B1_cnt4b[1] $ (!B1_cnt4b[3] & (B1_cnt4b[0]));
B1_cnt4b[1] = DFFEAS(B1_cnt4b[1]_lut_out, clk, !start, , , , , , );


--B1_cnt4b[0] is ARICTL:inst|cnt4b[0]
--operation mode is normal

B1_cnt4b[0]_lut_out = B1_cnt4b[3] $ !B1_cnt4b[0];
B1_cnt4b[0] = DFFEAS(B1_cnt4b[0]_lut_out, clk, !start, , , , , , );


--B1L2 is ARICTL:inst|clkout~24
--operation mode is normal

B1L2 = clk & (!B1_cnt4b[3] & !start);


--C1_reg8[0] is SREG8B:inst1|reg8[0]
--operation mode is normal

C1_reg8[0]_lut_out = C1_reg8[1];
C1_reg8[0] = DFFEAS(C1_reg8[0]_lut_out, B1L2, VCC, , , a[0], start, , );


--F1_dout[7] is ANDARITH:inst4|dout[7]
--operation mode is normal

F1_dout[7] = C1_reg8[0] & b[7];


--F1_dout[6] is ANDARITH:inst4|dout[6]
--operation mode is normal

F1_dout[6] = C1_reg8[0] & b[6];


--F1_dout[5] is ANDARITH:inst4|dout[5]
--operation mode is normal

F1_dout[5] = C1_reg8[0] & b[5];


--F1_dout[4] is ANDARITH:inst4|dout[4]
--operation mode is normal

F1_dout[4] = C1_reg8[0] & b[4];


--F1_dout[3] is ANDARITH:inst4|dout[3]
--operation mode is normal

F1_dout[3] = C1_reg8[0] & b[3];


--F1_dout[2] is ANDARITH:inst4|dout[2]
--operation mode is normal

F1_dout[2] = C1_reg8[0] & b[2];


--F1_dout[1] is ANDARITH:inst4|dout[1]
--operation mode is normal

F1_dout[1] = C1_reg8[0] & b[1];


--F1_dout[0] is ANDARITH:inst4|dout[0]
--operation mode is normal

F1_dout[0] = C1_reg8[0] & b[0];


--C1_reg8[1] is SREG8B:inst1|reg8[1]
--operation mode is normal

C1_reg8[1]_lut_out = C1_reg8[2];
C1_reg8[1] = DFFEAS(C1_reg8[1]_lut_out, B1L2, VCC, , , a[1], start, , );


--C1_reg8[2] is SREG8B:inst1|reg8[2]
--operation mode is normal

C1_reg8[2]_lut_out = C1_reg8[3];
C1_reg8[2] = DFFEAS(C1_reg8[2]_lut_out, B1L2, VCC, , , a[2], start, , );


--C1_reg8[3] is SREG8B:inst1|reg8[3]
--operation mode is normal

C1_reg8[3]_lut_out = C1_reg8[4];
C1_reg8[3] = DFFEAS(C1_reg8[3]_lut_out, B1L2, VCC, , , a[3], start, , );


--C1_reg8[4] is SREG8B:inst1|reg8[4]
--operation mode is normal

C1_reg8[4]_lut_out = C1_reg8[5];
C1_reg8[4] = DFFEAS(C1_reg8[4]_lut_out, B1L2, VCC, , , a[4], start, , );


--C1_reg8[5] is SREG8B:inst1|reg8[5]
--operation mode is normal

C1_reg8[5]_lut_out = C1_reg8[6];
C1_reg8[5] = DFFEAS(C1_reg8[5]_lut_out, B1L2, VCC, , , a[5], start, , );


--C1_reg8[6] is SREG8B:inst1|reg8[6]
--operation mode is normal

C1_reg8[6]_lut_out = C1_reg8[7];
C1_reg8[6] = DFFEAS(C1_reg8[6]_lut_out, B1L2, VCC, , , a[6], start, , );


--C1_reg8[7] is SREG8B:inst1|reg8[7]
--operation mode is normal

C1_reg8[7] = start & a[7] # !start & (C1_reg8[7]);


--start is start
--operation mode is input

start = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--b[7] is b[7]
--operation mode is input

b[7] = INPUT();


--b[6] is b[6]
--operation mode is input

b[6] = INPUT();


--b[5] is b[5]
--operation mode is input

b[5] = INPUT();


--b[4] is b[4]
--operation mode is input

b[4] = INPUT();


--b[3] is b[3]
--operation mode is input

b[3] = INPUT();


--b[2] is b[2]
--operation mode is input

b[2] = INPUT();


--b[1] is b[1]
--operation mode is input

b[1] = INPUT();


--b[0] is b[0]
--operation mode is input

b[0] = INPUT();


--a[0] is a[0]
--operation mode is input

a[0] = INPUT();


--a[1] is a[1]
--operation mode is input

a[1] = INPUT();


--a[2] is a[2]
--operation mode is input

a[2] = INPUT();


--a[3] is a[3]
--operation mode is input

a[3] = INPUT();


--a[4] is a[4]
--operation mode is input

a[4] = INPUT();


--a[5] is a[5]
--operation mode is input

a[5] = INPUT();


--a[6] is a[6]
--operation mode is input

a[6] = INPUT();


--a[7] is a[7]
--operation mode is input

a[7] = INPUT();


--ariend is ariend
--operation mode is output

ariend = OUTPUT(B1L1);


--dtout[15] is dtout[15]
--operation mode is output

dtout[15] = OUTPUT(E1_r16s[15]);


--dtout[14] is dtout[14]
--operation mode is output

dtout[14] = OUTPUT(E1_r16s[14]);


--dtout[13] is dtout[13]
--operation mode is output

dtout[13] = OUTPUT(E1_r16s[13]);


--dtout[12] is dtout[12]
--operation mode is output

dtout[12] = OUTPUT(E1_r16s[12]);


--dtout[11] is dtout[11]
--operation mode is output

dtout[11] = OUTPUT(E1_r16s[11]);


--dtout[10] is dtout[10]
--operation mode is output

dtout[10] = OUTPUT(E1_r16s[10]);


--dtout[9] is dtout[9]
--operation mode is output

dtout[9] = OUTPUT(E1_r16s[9]);


--dtout[8] is dtout[8]
--operation mode is output

dtout[8] = OUTPUT(E1_r16s[8]);


--dtout[7] is dtout[7]
--operation mode is output

dtout[7] = OUTPUT(E1_r16s[7]);


--dtout[6] is dtout[6]
--operation mode is output

dtout[6] = OUTPUT(E1_r16s[6]);


--dtout[5] is dtout[5]
--operation mode is output

dtout[5] = OUTPUT(E1_r16s[5]);


--dtout[4] is dtout[4]
--operation mode is output

dtout[4] = OUTPUT(E1_r16s[4]);


--dtout[3] is dtout[3]
--operation mode is output

dtout[3] = OUTPUT(E1_r16s[3]);


--dtout[2] is dtout[2]
--operation mode is output

dtout[2] = OUTPUT(E1_r16s[2]);


--dtout[1] is dtout[1]
--operation mode is output

dtout[1] = OUTPUT(E1_r16s[1]);


--dtout[0] is dtout[0]
--operation mode is output

dtout[0] = OUTPUT(E1_r16s[0]);