multi8x8.map.rpt

VHDL实现的8位乘法器

+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 38    ;
;     -- Combinational with no register       ; 11    ;
;     -- Register only                        ; 14    ;
;     -- Combinational with a register        ; 13    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 2     ;
;     -- 3 input functions                    ; 10    ;
;     -- 2 input functions                    ; 11    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 30    ;
;     -- arithmetic mode                      ; 8     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 27    ;
;                                             ;       ;
; Total registers                             ; 27    ;
; Total logic cells in carry chains           ; 9     ;
; I/O pins                                    ; 35    ;
; Maximum fan-out node                        ; start ;
; Maximum fan-out                             ; 30    ;
; Total fan-out                               ; 153   ;
; Average fan-out                             ; 2.10  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name      ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
; |multi8x8                  ; 38 (0)      ; 27           ; 0           ; 35   ; 0            ; 11 (0)       ; 14 (0)            ; 13 (0)           ; 9 (0)           ; 0 (0)      ; |multi8x8                ;
;    |ANDARITH:inst4|        ; 8 (8)       ; 0            ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |multi8x8|ANDARITH:inst4 ;
;    |ARICTL:inst|           ; 6 (6)       ; 4            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |multi8x8|ARICTL:inst    ;
;    |REG16B:inst3|          ; 16 (16)     ; 16           ; 0           ; 0    ; 0            ; 0 (0)        ; 7 (7)             ; 9 (9)            ; 9 (9)           ; 0 (0)      ; |multi8x8|REG16B:inst3   ;
;    |SREG8B:inst1|          ; 8 (8)       ; 7            ; 0           ; 0    ; 0            ; 1 (1)        ; 7 (7)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |multi8x8|SREG8B:inst1   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; SREG8B:inst1|reg8[7]                          ;   ;
; Number of user-specified and inferred latches ; 1 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 20    ;
; Number of registers using Asynchronous Load  ; 7     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/study/multi8x8/multi8x8.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Mar 29 12:10:03 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off multi8x8 -c multi8x8
Info: Found 1 design units, including 1 entities, in source file multi8x8.bdf
    Info: Found entity 1: multi8x8
Info: Found 2 design units, including 1 entities, in source file ARICTL.vhd
    Info: Found design unit 1: ARICTL-ARICTL_architecture
    Info: Found entity 1: ARICTL
Info: Found 2 design units, including 1 entities, in source file SREG8B.vhd
    Info: Found design unit 1: SREG8B-SREG8B_architecture
    Info: Found entity 1: SREG8B
Info: Found 2 design units, including 1 entities, in source file ANDARITH.vhd
    Info: Found design unit 1: ANDARITH-ANDARITH_architecture
    Info: Found entity 1: ANDARITH
Info: Found 2 design units, including 1 entities, in source file ADDER8B.vhd
    Info: Found design unit 1: ADDER8B-bdf_type
    Info: Found entity 1: ADDER8B
Info: Found 2 design units, including 1 entities, in source file REG16B.vhd
    Info: Found design unit 1: REG16B-REG16B_architecture
    Info: Found entity 1: REG16B
Info: Elaborating entity "multi8x8" for the top level hierarchy
Info: Elaborating entity "ARICTL" for hierarchy "ARICTL:inst"
Info: Elaborating entity "REG16B" for hierarchy "REG16B:inst3"
Info: Elaborating entity "ADDER8B" for hierarchy "ADDER8B:inst2"
Warning: Using design file add4b.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: add4b-add4b_architecture
    Info: Found entity 1: add4b
Info: Elaborating entity "add4b" for hierarchy "ADDER8B:inst2|add4b:b2v_inst"
Info: Elaborating entity "ANDARITH" for hierarchy "ANDARITH:inst4"
Info: Elaborating entity "SREG8B" for hierarchy "SREG8B:inst1"
Warning (10492): VHDL Process Statement warning at SREG8B.vhd(52): signal "din" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at SREG8B.vhd(49): signal or variable "reg8" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "reg8" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Implemented 73 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 17 output pins
    Info: Implemented 38 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Processing ended: Sat Mar 29 12:10:04 2008
    Info: Elapsed time: 00:00:02