sreg8b.vhd

VHDL实现的8位乘法器

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2006 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
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-- Generated by Quartus II Version 5.1 (Build Build 213 01/19/2006)
-- Created on Sat Mar 29 10:35:43 2008

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY SREG8B IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk : IN STD_LOGIC;
		load : IN STD_LOGIC;
		din : IN STD_LOGIC_VECTOR(7 downto 0);
		qb : OUT STD_LOGIC
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END SREG8B;


--  Architecture Body

ARCHITECTURE SREG8B_architecture OF SREG8B IS
signal reg8:std_logic_vector(7 downto 0);
	
BEGIN
 process(clk,load)
  begin
   if load='1' then
      reg8<=din;
   elsif rising_edge(clk) then
      reg8(6 downto 0)<=reg8(7 downto 1);
   end if;
 end process;
 qb<=reg8(0);
END SREG8B_architecture;