h.264.mpf

H.264标准解码器全部verilog源码

; yielding the performance / behavior of the prior release.
; Default value set to "" (random compatibility not required).
; SolveRev = ""

; Environment variable expansion of command line arguments has been depricated 
; in favor shell level expansion.  Universal environment variable expansion 
; inside -f files is support and continued support for MGC Location Maps provide
; alternative methods for handling flexible pathnames.
; The following line may be uncommented and the value set to 1 to re-enable this 
; deprecated behavior.  The default value is 0.
; DeprecatedEnvironmentVariableExpansion = 0

; Retroactive Recording uses a limited number of private data channels in the WLF
; file.  Too many channels degrade WLF performance.  If the limit is reached, 
; simulation ends with a fatal error.  You may change this limit as needed, but be
; aware of the implications of too many channels.  The value must be an integer
; greater than or equal to zero, where zero disables all retroactive recording.
; RetroChannelLimit = 20

; Options to give vopt when code coverage is turned on.
; Default is "+acc=lprnb -opt=-merge -opt=-suppressAlways"
; VoptCoverageOptions = +acc=lprnb -opt=-merge -opt=-suppressAlways

[lmc]
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
;  Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
;  Logic Modeling's SmartModel SWIFT software (Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so

; The simulator's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
;  Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
;  Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so

[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
;   note = 3009
;   warning = 3033
;   error = 3010,3016
;   fatal = 3016,3033
;   suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.

; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and 
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer).  The other settings
; are to send messages only to the transcript or only to the 
; wlf file.  The valid values are
;    both  {default}
;    tran  {transcript only}
;    wlf   {wlf file only}
; msgmode = both
[Project]
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 56
Project_File_0 = E:/Verilog/H.264/BitStream_controller.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = E:/Verilog/H.264/DF_pipeline.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = E:/Verilog/H.264/timescale.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = E:/Verilog/H.264/nova_defines.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 vlog_noload 0 folder {Top Level} last_compile 1209527914 cover_fsm 0 cover_branch 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 47 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = E:/Verilog/H.264/Intra_pred_reg_ctrl.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1209527910 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 54 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = E:/Verilog/H.264/Inter_pred_LPE.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 35 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = E:/Verilog/H.264/nova.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 46 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = E:/Verilog/H.264/Intra_pred_pipeline.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 last_compile 1235486763 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 41 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = E:/Verilog/H.264/rec_DF_RAM_ctrl.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = E:/Verilog/H.264/exp_golomb_decoding.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 27 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = E:/Verilog/H.264/Beha_BitStream_ram.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = E:/Verilog/H.264/nova_tb.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 48 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = E:/Verilog/H.264/reconstruction.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = E:/Verilog/H.264/rec_DF_RAM1_wrapper.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = E:/Verilog/H.264/bitstream_gclk_gen.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = E:/Verilog/H.264/Inter_pred_sliding_window.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 38 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = E:/Verilog/H.264/nC_decoding.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 45 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = E:/Verilog/H.264/NumCoeffTrailingOnes_decoding.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 49 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = E:/Verilog/H.264/Inter_pred_top.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 39 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_19 = E:/Verilog/H.264/dependent_variable_decoding.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = E:/Verilog/H.264/heading_one_detector.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 31 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = E:/Verilog/H.264/Intra_pred_top.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 last_compile 1209527912 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 42 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_22 = E:/Verilog/H.264/syntax_decoding.v
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_23 = E:/Verilog/H.264/rec_gclk_gen.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_24 = E:/Verilog/H.264/Intra_pred_PE.v
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 last_compile 1209527910 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 53 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_25 = E:/Verilog/H.264/CodedBlockPattern_decoding.v
Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_26 = E:/Verilog/H.264/QP_decoding.v
Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 51 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_27 = E:/Verilog/H.264/run_decoding.v
Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_28 = E:/Verilog/H.264/Intra4x4_PredMode_decoding.v
Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1209527908 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 40 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_29 = E:/Verilog/H.264/ext_frame_RAM0_wrapper.v
Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 28 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_30 = E:/Verilog/H.264/Inter_pred_CPE.v
Project_File_P_30 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 34 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_31 = E:/Verilog/H.264/Inter_pred_reg_ctrl.v
Project_File_P_31 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 vlog_noload 0 folder {Top Level} last_compile 1209527902 cover_fsm 0 cover_branch 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 37 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_32 = E:/Verilog/H.264/Inter_pred_pipeline.v
Project_File_P_32 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 36 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_33 = E:/Verilog/H.264/total_zeros_decoding.v
Project_File_P_33 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_34 = E:/Verilog/H.264/hybrid_pipeline_ctrl.v
Project_File_P_34 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 32 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_35 = E:/Verilog/H.264/DF_mem_ctrl.v
Project_File_P_35 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_36 = E:/Verilog/H.264/rec_DF_RAM0_96x32.v
Project_File_P_36 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_37 = E:/Verilog/H.264/rec_DF_RAM1_96x32.v
Project_File_P_37 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_38 = E:/Verilog/H.264/cavlc_decoder.v
Project_File_P_38 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 0 cover_fsm 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_39 = E:/Verilog/H.264/ram_sync_1r_sync_1w.v
Project_File_P_39 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1209527914 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 1 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 55 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_40 = E:/Verilog/H.264/cavlc_consumed_bits_decoding.v
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Project_File_43 = E:/Verilog/H.264/pc_decoding.v
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Project_File_45 = E:/Verilog/H.264/BitStream_parser_FSM_gating.v
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Project_File_46 = E:/Verilog/H.264/end_of_blk_decoding.v
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Project_File_47 = E:/Verilog/H.264/IQIT.v
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Project_File_48 = E:/Verilog/H.264/Inter_mv_decoding.v
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Project_File_49 = E:/Verilog/H.264/rec_DF_RAM0_wrapper.v
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Project_File_50 = E:/Verilog/H.264/ram_async_1r_sync_1w.v
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Project_File_51 = E:/Verilog/H.264/DF_reg_ctrl.v
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Project_File_52 = E:/Verilog/H.264/level_decoding.v
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Project_File_53 = E:/Verilog/H.264/ext_RAM_ctrl.v
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Project_File_54 = E:/Verilog/H.264/DF_top.v
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Project_File_55 = E:/Verilog/H.264/BitStream_buffer.v
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Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
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ForceSoftPaths = 0
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VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick = 
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick = 
PSL_DoubleClick = Edit
PSL_CustomDoubleClick = 
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick = 
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick = 
TCL_DoubleClick = Edit
TCL_CustomDoubleClick = 
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick = 
VCD_DoubleClick = Edit
VCD_CustomDoubleClick = 
SDF_DoubleClick = Edit
SDF_CustomDoubleClick = 
XML_DoubleClick = Edit
XML_CustomDoubleClick = 
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick = 
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Project_Major_Version = 6
Project_Minor_Version = 2