intra_pred_pe.srr

H.264标准解码器全部verilog源码

Buffering Intra4x4_predmode_c[3], fanout 25 segments 3
Buffering Intra4x4_predmode_c[2], fanout 59 segments 5
Buffering Intra4x4_predmode_c[1], fanout 34 segments 3
Buffering Intra4x4_predmode_c[0], fanout 61 segments 6
Buffering blk4x4_intra_calculate_counter_c[2], fanout 113 segments 10
Buffering blk4x4_intra_calculate_counter_c[1], fanout 165 segments 14
Buffering blk4x4_intra_calculate_counter_c[0], fanout 121 segments 11
Buffering blk4x4_rec_counter_c[4], fanout 56 segments 5
Buffering blk4x4_rec_counter_c[2], fanout 25 segments 3
Buffering mb_type_general_c[3], fanout 26 segments 3
Buffering mb_type_general_c[2], fanout 31 segments 3
Buffering reset_n_c, fanout 64 segments 6
Replicating N_6722_0, fanout 13 segments 2
Replicating N_6056_3, fanout 13 segments 2
Replicating N_418_1_2, fanout 16 segments 2
Replicating N_418_1_1, fanout 14 segments 2
Replicating N_418_1_0, fanout 15 segments 2
Replicating N_6400_0, fanout 15 segments 2
Replicating PE1_shift_len_0[2], fanout 14 segments 2
Replicating N_6089, fanout 16 segments 2
Replicating PE0_in0_0_sqmuxa_4_1, fanout 15 segments 2
Replicating N_6099, fanout 19 segments 2
Replicating N_6155, fanout 29 segments 3
Replicating N_4889, fanout 17 segments 2
Replicating N_6066, fanout 13 segments 2
Replicating N_5698, fanout 18 segments 2
Replicating N_5222, fanout 15 segments 2
Replicating N_6442, fanout 14 segments 2
Buffering Intra4x4_predmode_c[2], fanout 15 segments 2
Buffering blk4x4_intra_calculate_counter_c[2], fanout 14 segments 2
Buffering blk4x4_intra_calculate_counter_c[1], fanout 22 segments 2
Buffering blk4x4_intra_calculate_counter_c[0], fanout 21 segments 2
Buffering reset_n_c, fanout 14 segments 2
Replicating N_3076_i_i_0, fanout 13 segments 2
Buffering mbAddrA_availability_c, fanout 13 segments 2
Buffering Intra16x16_predmode_c[1], fanout 13 segments 2
Buffering blk4x4_rec_counter_c[4], fanout 13 segments 2
Replicating mb_type_general_c_0[2], fanout 14 segments 2
Replicating blk4x4_rec_counter_c_0[4], fanout 16 segments 2
Replicating blk4x4_intra_calculate_counter_c_1[1], fanout 13 segments 2
Replicating blk4x4_intra_calculate_counter_c_0[1], fanout 13 segments 2
Replicating blk4x4_intra_calculate_counter_c_3[2], fanout 13 segments 2
Replicating blk4x4_intra_calculate_counter_c_0[2], fanout 13 segments 2

Added 71 Buffers
Added 244 Cells via replication
Writing Analyst data base E:\Verilog\H.264\rev_1\Intra_pred_PE.srm
Writing EDIF Netlist and constraint files
Found clock Intra_pred_PE|clk with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Sun Feb 22 14:06:47 2009
#


Top view:               Intra_pred_PE
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 951.915

                      Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock        Frequency     Frequency     Period        Period        Slack       Type         Group              
--------------------------------------------------------------------------------------------------------------------------
Intra_pred_PE|clk     1.0 MHz       20.8 MHz      1000.000      48.085        951.915     inferred     Inferred_clkgroup_0
==========================================================================================================================





Clock Relationships
*******************

Clocks                                |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
------------------------------------------------------------------------------------------------------------------------------
Starting           Ending             |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------
Intra_pred_PE|clk  Intra_pred_PE|clk  |  1000.000    951.915  |  No paths    -      |  No paths    -      |  No paths    -    
==============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: Intra_pred_PE|clk
====================================



Starting Points with Worst Slack
********************************

                      Starting                                                  Arrival            
Instance              Reference             Type     Pin     Net                Time        Slack  
                      Clock                                                                        
---------------------------------------------------------------------------------------------------
PE2.PE_out_reg[0]     Intra_pred_PE|clk     DFF      Q       PE2_out_reg[0]     0.200       951.915
PE3.PE_out_reg[0]     Intra_pred_PE|clk     DFF      Q       PE3_out_reg[0]     0.200       952.263
PE2.PE_out_reg[1]     Intra_pred_PE|clk     DFF      Q       PE2_out_reg[1]     0.200       953.001
PE3.PE_out_reg[1]     Intra_pred_PE|clk     DFF      Q       PE3_out_reg[1]     0.200       953.971
PE2.PE_out_reg[2]     Intra_pred_PE|clk     DFF      Q       PE2_out_reg[2]     0.200       954.601
PE3.PE_out_reg[2]     Intra_pred_PE|clk     DFF      Q       PE3_out_reg[2]     0.200       956.487
PE1.PE_out_reg[0]     Intra_pred_PE|clk     DFF      Q       PE1_out_reg[0]     0.200       956.594
PE0.PE_out_reg[0]     Intra_pred_PE|clk     DFF      Q       PE0_out_reg[0]     0.200       957.510
PE2.PE_out_reg[3]     Intra_pred_PE|clk     DFF      Q       PE2_out_reg[3]     0.200       957.617
PE1.PE_out_reg[1]     Intra_pred_PE|clk     DFF      Q       PE1_out_reg[1]     0.200       957.676
===================================================================================================


Ending Points with Worst Slack
******************************

                       Starting                                                           Required            
Instance               Reference             Type     Pin     Net                         Time         Slack  
                       Clock                                                                                  
--------------------------------------------------------------------------------------------------------------
PE0.PE_out_reg[15]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2[15]       999.752      951.915
PE0.PE_out_reg[14]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2[14]       999.752      953.487
PE3.PE_out_reg[15]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2_2[15]     999.752      954.444
PE2.PE_out_reg[15]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2_1[15]     999.752      955.604
PE0.PE_out_reg[13]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2[13]       999.752      955.791
PE3.PE_out_reg[14]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2_2[14]     999.752      956.744
PE0.PE_out_reg[12]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2[12]       999.752      957.229
PE2.PE_out_reg[14]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2_1[14]     999.752      957.894
PE1.PE_out_reg[15]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2_0[15]     999.752      958.136
PE3.PE_out_reg[13]     Intra_pred_PE|clk     DFF      D       PE_out_reg_1_0_a2_2[13]     999.752      958.182
==============================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    - Setup time:                            0.248
    = Required time:                         999.752

    - Propagation time:                      47.837
    = Slack (critical) :                     951.915

    Number of logic level(s):                42
    Starting point:                          PE2.PE_out_reg[0] / Q
    Ending point:                            PE0.PE_out_reg[15] / D
    The start point is clocked by            Intra_pred_PE|clk [rising] on pin CLK
    The end   point is clocked by            Intra_pred_PE|clk [rising] on pin CLK

Instance / Net                                                    Pin      Pin               Arrival     No. of    
Name                                                 Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
PE2.PE_out_reg[0]                                    DFF          Q        Out     0.200     0.200       -         
PE2_out_reg[0]                                       Net          -        -       1.480     -           3         
PE2_out_reg_m[0]                                     AND2         B        In      -         1.680       -         
PE2_out_reg_m[0]                                     AND2         Y        Out     0.164     1.844       -         
PE2_out_reg_m_i[0]                                   Net          -        -       0.630     -           1         
PE0_in2_r[0]                                         OA21         A        In      -         2.474       -         
PE0_in2_r[0]                                         OA21         Y        Out     0.116     2.590       -         
PE0_in2[0]                                           Net          -        -       1.480     -           3         
PE0.un2_sum_out_0.ADD_16x16_slow_I0_un1_CO1          AND2         A        In      -         4.070       -         
PE0.un2_sum_out_0.ADD_16x16_slow_I0_un1_CO1          AND2         Y        Out     0.108     4.178       -         
I0_un1_CO1_1                                         Net          -        -       1.480     -           3