intra_pred_pe.srs

H.264标准解码器全部verilog源码

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Sun Feb 22 14:06:04 2009
#
#
#OPTIONS:"|-I|E:\\Verilog\\H.264\\|-I|C:\\Program Files\\Synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\Program Files\\Synplicity\\fpga_81\\lib\\proasic\\proasic.v|-autosm|-fid2|-sharing|on|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\Program Files\\Synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\Program Files\\Synplicity\\fpga_81\\lib\\proasic\\proasic.v":1072685752
#CUR:"C:\\Program Files\\Synplicity\\fpga_81\\lib\\proasic\\proasic.v":1072685752
#CUR:"E:\\Verilog\\H.264\\Intra_pred_PE.v":1209527910
#CUR:"E:\\Verilog\\H.264\\Intra_pred_PE.v":1209527910
#CUR:"E:\\Verilog\\H.264\\nova_defines.v":1209527914
#CUR:"E:\\Verilog\\H.264\\nova_defines.v":1209527914
f "C:\Program Files\Synplicity\fpga_81\lib\proasic\proasic.v"; # file 0
af .is_verilog 1;
f "E:\Verilog\H.264\Intra_pred_PE.v"; # file 1
af .is_verilog 1;
f "E:\Verilog\H.264\nova_defines.v"; # file 2
af .is_verilog 1;
@E
@ 
ftell;
@E@MR@44:6:UU(6:4UUU:RsIF	 RuRsPCHoDF;P
NR#3HPHCsDRFo4N;
PHR3#C_PsFHDo;R4
RNP3HFsolhNCuR" 
";
@HR@44:6:gj(6:4ggj:R	ODR	OD;



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;

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R4@@:g46c::(4c6g:R4.HRMPk_M4QD#BHkbRMQ4_#HBDb#RQBbDH;R
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b@:@44.n4::4n4.n4:R(dlRkGknM4_l#k.6r4:Rj9knM4_l#k.6r4:Rj9kjM4_l#k.6r4:Rj9HrM.4jc:9N,VD
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#CRRRRVDkD_bL$N;##
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j9RRRRORD	k_M4sCC#0R_MQ0#1F;sC
RNH3M#$_FbsOlMNCbR"s_FOuF _ks0_C;o"
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R4@@:g466::(466g:R4(NPM8RHODbk_F0__j#kJlGONRD_HbF_k0jJ_#lNkGRBQ#DRHbsMFk8k_F06r49R
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0;b@R@46:4g(6::g466(:4R8NMPDROHFb_k.0__l#JkRGNObDH_0Fk_#._JGlkNMRk6D_OHFb_kk0RMO4_D_HbF
k0RRRRk_M4VDkD_bL$N;##
@bR@44:n:.d.4j:n:.c.F.RskPRMO4_D_HbF_k04MRk4D_OHFb_k40_R.kMdD_OHFb_kk0RMQ4_#HBDbb;
R4@@:g466::(466g:R4(NPM8RHODbk_F0__4#kJlGONRD_HbF_k04J_#lNkGR4kM_HODbk_F0R_4k_M4VDkD_bL$N;##
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---------------------------------@-
 ftell;
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;

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