_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity Intra_pred_PE is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        mb_type_general : in     vl_logic_vector(3 downto 0);
        blk4x4_rec_counter: in     vl_logic_vector(4 downto 0);
        blk4x4_intra_calculate_counter: in     vl_logic_vector(2 downto 0);
        Intra4x4_predmode: in     vl_logic_vector(3 downto 0);
        Intra16x16_predmode: in     vl_logic_vector(1 downto 0);
        Intra_chroma_predmode: in     vl_logic_vector(1 downto 0);
        blkAddrA_availability: in     vl_logic;
        blkAddrB_availability: in     vl_logic;
        mbAddrA_availability: in     vl_logic;
        mbAddrB_availability: in     vl_logic;
        Intra_mbAddrA_window0: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_window1: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_window2: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_window3: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_window0: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_window1: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_window2: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_window3: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrC_window0: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrC_window1: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrC_window2: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrC_window3: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrD_window: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg0: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg1: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg2: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg3: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg4: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg5: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg6: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg7: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg8: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg9: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg10: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg11: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg12: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg13: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg14: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_reg15: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg0: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg1: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg2: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg3: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg4: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg5: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg6: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg7: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg8: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg9: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg10: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg11: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg12: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg13: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg14: in     vl_logic_vector(15 downto 0);
        Intra_mbAddrB_reg15: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output0: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output1: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output2: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output4: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output5: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output6: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output8: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output9: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output10: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output12: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output13: in     vl_logic_vector(15 downto 0);
        blk4x4_pred_output14: in     vl_logic_vector(15 downto 0);
        seed            : in     vl_logic_vector(15 downto 0);
        b               : in     vl_logic_vector(11 downto 0);
        c               : in     vl_logic_vector(11 downto 0);
        PE0_out         : out    vl_logic_vector(7 downto 0);
        PE1_out         : out    vl_logic_vector(7 downto 0);
        PE2_out         : out    vl_logic_vector(7 downto 0);
        PE3_out         : out    vl_logic_vector(7 downto 0);
        PE0_sum_out     : out    vl_logic_vector(15 downto 0);
        PE3_sum_out     : out    vl_logic_vector(15 downto 0)
    );
end Intra_pred_PE;