_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity Intra4x4_PredMode_decoding is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        mb_pred_state   : in     vl_logic_vector(2 downto 0);
        luma4x4BlkIdx   : in     vl_logic_vector(3 downto 0);
        mb_num_h        : in     vl_logic_vector(3 downto 0);
        mb_num_v        : in     vl_logic_vector(3 downto 0);
        MBTypeGen_mbAddrA: in     vl_logic_vector(1 downto 0);
        MBTypeGen_mbAddrB_reg: in     vl_logic_vector(21 downto 0);
        constrained_intra_pred_flag: in     vl_logic;
        rem_intra4x4_pred_mode: in     vl_logic_vector(2 downto 0);
        prev_intra4x4_pred_mode_flag: in     vl_logic;
        Intra4x4PredMode_mbAddrB_dout: in     vl_logic_vector(15 downto 0);
        Intra4x4PredMode_CurrMb: out    vl_logic_vector(63 downto 0);
        Intra4x4PredMode_mbAddrB_cs_n: out    vl_logic;
        Intra4x4PredMode_mbAddrB_wr_n: out    vl_logic;
        Intra4x4PredMode_mbAddrB_rd_addr: out    vl_logic_vector(3 downto 0);
        Intra4x4PredMode_mbAddrB_wr_addr: out    vl_logic_vector(3 downto 0);
        Intra4x4PredMode_mbAddrB_din: out    vl_logic_vector(15 downto 0)
    );
end Intra4x4_PredMode_decoding;