_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity Inter_pred_reg_ctrl is
    port(
        gclk_Inter_ref_rf: in     vl_logic;
        reset_n         : in     vl_logic;
        blk4x4_inter_preload_counter: in     vl_logic_vector(5 downto 0);
        ref_frame_RAM_dout: in     vl_logic_vector(31 downto 0);
        IsInterLuma     : in     vl_logic;
        IsInterChroma   : in     vl_logic;
        xInt_addr_unclip: in     vl_logic_vector(8 downto 0);
        xInt_org_unclip_1to0: in     vl_logic_vector(1 downto 0);
        pos_FracL       : in     vl_logic_vector(3 downto 0);
        xFracC          : in     vl_logic_vector(2 downto 0);
        yFracC          : in     vl_logic_vector(2 downto 0);
        mv_below8x8_curr: in     vl_logic;
        Inter_ref_00_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_00 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_01 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_02 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_03 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_04 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_05 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_06 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_07 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_08 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_09 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_10 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_11 : out    vl_logic_vector(7 downto 0);
        Inter_ref_00_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_01_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_02_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_03_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_04_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_05_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_06_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_07_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_08_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_09_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_10_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_11_12 : out    vl_logic_vector(7 downto 0);
        Inter_ref_12_12 : out    vl_logic_vector(7 downto 0)
    );
end Inter_pred_reg_ctrl;