_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity Intra_pred_pipeline is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        mb_type_general : in     vl_logic_vector(3 downto 0);
        blk4x4_rec_counter: in     vl_logic_vector(4 downto 0);
        trigger_blk4x4_intra_pred: in     vl_logic;
        mb_num_v        : in     vl_logic_vector(3 downto 0);
        mb_num_h        : in     vl_logic_vector(3 downto 0);
        blk4x4_sum_counter: in     vl_logic_vector(2 downto 0);
        NextMB_IsSkip   : in     vl_logic;
        Intra16x16_predmode: in     vl_logic_vector(1 downto 0);
        Intra4x4_predmode_CurrMb: in     vl_logic_vector(63 downto 0);
        Intra_chroma_predmode: in     vl_logic_vector(1 downto 0);
        Intra_mbAddrA_reg0: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg1: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg2: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg3: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg4: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg5: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg6: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg7: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg8: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg9: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg10: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg11: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg12: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg13: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg14: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg15: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg0: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg1: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg2: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg3: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg4: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg5: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg6: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg7: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg8: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg9: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg10: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg11: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg12: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg13: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg14: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg15: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrD_window: in     vl_logic_vector(7 downto 0);
        Intra4x4_predmode: out    vl_logic_vector(3 downto 0);
        blk4x4_intra_preload_counter: out    vl_logic_vector(2 downto 0);
        blk4x4_intra_precompute_counter: out    vl_logic_vector(3 downto 0);
        blk4x4_intra_calculate_counter: out    vl_logic_vector(2 downto 0);
        end_of_one_blk4x4_intra: out    vl_logic;
        blkAddrA_availability: out    vl_logic;
        blkAddrB_availability: out    vl_logic;
        mbAddrA_availability: out    vl_logic;
        mbAddrB_availability: out    vl_logic;
        mbAddrC_availability: out    vl_logic;
        main_seed       : out    vl_logic_vector(15 downto 0);
        plane_b_reg     : out    vl_logic_vector(11 downto 0);
        plane_c_reg     : out    vl_logic_vector(11 downto 0);
        Intra_mbAddrB_RAM_rd: out    vl_logic;
        Intra_mbAddrB_RAM_rd_addr: out    vl_logic_vector(6 downto 0)
    );
end Intra_pred_pipeline;