_primary.vhd

来自「H.264标准解码器全部verilog源码」· VHDL 代码 · 共 19 行

library verilog;
use verilog.vl_types.all;
entity ram_sync_1r_sync_1w is
    generic(
        data_width      : integer := 4;
        data_depth      : integer := 8
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        wr_n            : in     vl_logic;
        rd_n            : in     vl_logic;
        wr_addr         : in     vl_logic_vector;
        rd_addr         : in     vl_logic_vector;
        data_in         : in     vl_logic_vector;
        data_out        : out    vl_logic_vector
    );
end ram_sync_1r_sync_1w;