_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity PE is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        in0             : in     vl_logic_vector(15 downto 0);
        in1             : in     vl_logic_vector(15 downto 0);
        in2             : in     vl_logic_vector(15 downto 0);
        in3             : in     vl_logic_vector(15 downto 0);
        IsShift         : in     vl_logic;
        IsStore         : in     vl_logic;
        IsClip          : in     vl_logic;
        full_bypass     : in     vl_logic;
        round_value     : in     vl_logic_vector(4 downto 0);
        shift_len       : in     vl_logic_vector(2 downto 0);
        PE_out_reg      : out    vl_logic_vector(15 downto 0);
        PE_out          : out    vl_logic_vector(7 downto 0);
        sum_out         : out    vl_logic_vector(15 downto 0)
    );
end PE;