_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity Intra_pred_reg_ctrl is
    port(
        reset_n         : in     vl_logic;
        gclk_intra_mbAddrA_luma: in     vl_logic;
        gclk_intra_mbAddrA_Cb: in     vl_logic;
        gclk_intra_mbAddrA_Cr: in     vl_logic;
        gclk_intra_mbAddrB: in     vl_logic;
        gclk_intra_mbAddrC_luma: in     vl_logic;
        gclk_intra_mbAddrD: in     vl_logic;
        gclk_seed       : in     vl_logic;
        mbAddrA_availability: in     vl_logic;
        mbAddrC_availability: in     vl_logic;
        blk4x4_rec_counter: in     vl_logic_vector(4 downto 0);
        blk4x4_sum_counter: in     vl_logic_vector(2 downto 0);
        blk4x4_intra_preload_counter: in     vl_logic_vector(2 downto 0);
        blk4x4_intra_precompute_counter: in     vl_logic_vector(3 downto 0);
        blk4x4_intra_calculate_counter: in     vl_logic_vector(2 downto 0);
        mb_type_general : in     vl_logic_vector(3 downto 0);
        Intra4x4_predmode: in     vl_logic_vector(3 downto 0);
        Intra16x16_predmode: in     vl_logic_vector(1 downto 0);
        Intra_chroma_predmode: in     vl_logic_vector(1 downto 0);
        Intra_mbAddrB_RAM_dout: in     vl_logic_vector(31 downto 0);
        sum_right_column_reg: in     vl_logic_vector(23 downto 0);
        blk4x4_sum_PE0_out: in     vl_logic_vector(7 downto 0);
        blk4x4_sum_PE1_out: in     vl_logic_vector(7 downto 0);
        blk4x4_sum_PE2_out: in     vl_logic_vector(7 downto 0);
        blk4x4_sum_PE3_out: in     vl_logic_vector(7 downto 0);
        main_seed       : in     vl_logic_vector(15 downto 0);
        PE0_sum_out     : in     vl_logic_vector(15 downto 0);
        PE3_sum_out     : in     vl_logic_vector(15 downto 0);
        Intra_mbAddrA_window0: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_window1: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_window2: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_window3: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg0: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg1: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg2: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg3: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg4: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg5: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg6: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg7: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg8: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg9: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg10: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg11: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg12: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg13: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg14: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrA_reg15: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_window0: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_window1: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_window2: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_window3: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg0: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg1: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg2: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg3: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg4: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg5: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg6: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg7: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg8: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg9: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg10: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg11: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg12: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg13: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg14: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrB_reg15: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrC_window0: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrC_window1: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrC_window2: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrC_window3: out    vl_logic_vector(7 downto 0);
        Intra_mbAddrD_window: out    vl_logic_vector(7 downto 0);
        seed            : out    vl_logic_vector(15 downto 0)
    );
end Intra_pred_reg_ctrl;