_primary.vhd

H.264标准解码器全部verilog源码

library verilog;
use verilog.vl_types.all;
entity Intra_pred_top is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        gclk_intra_mbAddrA_luma: in     vl_logic;
        gclk_intra_mbAddrA_Cb: in     vl_logic;
        gclk_intra_mbAddrA_Cr: in     vl_logic;
        gclk_intra_mbAddrB: in     vl_logic;
        gclk_intra_mbAddrC_luma: in     vl_logic;
        gclk_intra_mbAddrD: in     vl_logic;
        gclk_seed       : in     vl_logic;
        gclk_Intra_mbAddrB_RAM: in     vl_logic;
        mb_num_h        : in     vl_logic_vector(3 downto 0);
        mb_num_v        : in     vl_logic_vector(3 downto 0);
        mb_type_general : in     vl_logic_vector(3 downto 0);
        NextMB_IsSkip   : in     vl_logic;
        Intra16x16_predmode: in     vl_logic_vector(1 downto 0);
        Intra4x4_predmode_CurrMb: in     vl_logic_vector(63 downto 0);
        Intra_chroma_predmode: in     vl_logic_vector(1 downto 0);
        blk4x4_rec_counter: in     vl_logic_vector(4 downto 0);
        trigger_blk4x4_intra_pred: in     vl_logic;
        blk4x4_sum_counter: in     vl_logic_vector(2 downto 0);
        sum_right_column_reg: in     vl_logic_vector(23 downto 0);
        blk4x4_sum_PE0_out: in     vl_logic_vector(7 downto 0);
        blk4x4_sum_PE1_out: in     vl_logic_vector(7 downto 0);
        blk4x4_sum_PE2_out: in     vl_logic_vector(7 downto 0);
        blk4x4_sum_PE3_out: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output0: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output1: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output2: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output4: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output5: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output6: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output8: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output9: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output10: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output12: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output13: in     vl_logic_vector(7 downto 0);
        blk4x4_pred_output14: in     vl_logic_vector(7 downto 0);
        Intra_mbAddrB_RAM_wr: in     vl_logic;
        Intra_mbAddrB_RAM_wr_addr: in     vl_logic_vector(6 downto 0);
        Intra_mbAddrB_RAM_din: in     vl_logic_vector(31 downto 0);
        PE0_out         : out    vl_logic_vector(7 downto 0);
        PE1_out         : out    vl_logic_vector(7 downto 0);
        PE2_out         : out    vl_logic_vector(7 downto 0);
        PE3_out         : out    vl_logic_vector(7 downto 0);
        Intra4x4_predmode: out    vl_logic_vector(3 downto 0);
        blk4x4_intra_preload_counter: out    vl_logic_vector(2 downto 0);
        blk4x4_intra_precompute_counter: out    vl_logic_vector(3 downto 0);
        blk4x4_intra_calculate_counter: out    vl_logic_vector(2 downto 0);
        end_of_one_blk4x4_intra: out    vl_logic;
        Intra_mbAddrB_RAM_rd: out    vl_logic
    );
end Intra_pred_top;