sseg.abl

FPGA的时钟设计,源代码,很有参考价值,希望对学习FPGA设计的朋友有参考意义.

MODULE sseg

TITLE 'seven segment decoder'

D0,D1,D2,D3       pin ;

A,B,C,D,E,F,G     pin istype 'com';



truth_table

	([D3,D2,D1,D0] -> [G,F,E,D,C,B,A])
         [ 0, 0, 0, 0] -> [0,1,1,1,1,1,1];
         [ 0, 0, 0, 1] -> [0,0,0,0,1,1,0];
         [ 0, 0, 1, 0] -> [1,0,1,1,0,1,1];
         [ 0, 0, 1, 1] -> [1,0,0,1,1,1,1];
         [ 0, 1, 0, 0] -> [1,1,0,0,1,1,0];
         [ 0, 1, 0, 1] -> [1,1,0,1,1,0,1];
         [ 0, 1, 1, 0] -> [1,1,1,1,1,0,1];
         [ 0, 1, 1, 1] -> [0,0,0,0,1,1,1];
         [ 1, 0, 0, 0] -> [1,1,1,1,1,1,1];
         [ 1, 0, 0, 1] -> [1,1,0,1,1,1,1];
         [ 1, 0, 1, 0] -> [1,0,0,0,0,0,0];
         [ 1, 0, 1, 1] -> [1,0,0,0,0,0,1];
         [ 1, 1, 0, 0] -> [1,0,0,1,0,0,1];
         [ 1, 1, 0, 1] -> [0,1,1,0,1,1,0];
         [ 1, 1, 1, 0] -> [1,1,1,0,1,1,0];
         [ 1, 1, 1, 1] -> [0,1,1,1,1,1,0];

END