clocktop.abv

FPGA的时钟设计,源代码,很有参考价值,希望对学习FPGA设计的朋友有参考意义.

module clocktop;

"Input pin declarations
SYSCLK	PIN;
nFAST	PIN;
nHOLD	PIN;
nSLOW	PIN;
TEST	PIN;

"Output pin declarations
COLON	PIN;
AM		PIN;
PM		PIN;
HSJ		PIN;
HSH		PIN;
HSG		PIN;
HSF		PIN;
HSE		PIN;
HSD		PIN;
HSC		PIN;
HSB		PIN;
HSA		PIN;

MTSG	PIN;
MTSF	PIN;
MTSE	PIN;
MTSD	PIN;
MTSC	PIN;
MTSB	PIN;
MTSA	PIN;

MUSG	PIN;
MUSF	PIN;
MUSE	PIN;
MUSD	PIN;
MUSC	PIN;
MUSB	PIN;
MUSA	PIN;

Test_Vectors([nFAST, nHOLD, nSLOW, TEST]->
[COLON,AM,PM,HSJ,HSH,HSG,HSF,HSE,HSD,HSC,HSB,HSA,MTSG,MTSF,MTSE,MTSD,MTSC,MTSB,MTSA,
 MUSG,MUSF,MUSE,MUSD,MUSC,MUSB,MUSA])

cycle SYSCLK (0, 10) (1, 10);
[0,0,0,1]->.X.;
WAIT 20; [1,1,1,1]-> .X.;
WAIT  3200; [1,1,0,1]->.X.;
WAIT 35200; [1,0,1,1]->.X.;
WAIT  6400; [1,1,1,1]->.X.;
WAIT 10520; [1,1,1,1]->.X.;


END;