📄 数字钟2.txt
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数字钟的VHDL设计
一、设计目的
1.掌握各类计数器及将它们相连的方法;
2.掌握多个数码管动态显示的原理与方法;
3.掌握用FPGA技术的层次化设计方法;
4.进一步掌握用VHDL硬件描述语言的设计思想;
5.了解有关数字系统的设计。
二、设计要求
基本要求:
1、24小时计数显示;
2、具有校时功能(时,分) ;
附加要求:
1、实现闹钟功能(定时,闹响);
三、程序代码
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity szz is
port(clk0:in std_logic;
md1:in std_logic;
md2:in std_logic_vector(1 downto 0);
speak:out std_logic;
dout:out std_logic_vector(6 downto 0);
selout:out std_logic_vector(5 downto 0));
end szz;
architecture one of szz is
signal sel:std_logic_vector(2 downto 0);
signal hou1:std_logic_vector(3 downto 0);
signal hou2:std_logic_vector(3 downto 0);
signal min1:std_logic_vector(3 downto 0);
signal min2:std_logic_vector(3 downto 0);
signal seth1:std_logic_vector(3 downto 0);
signal seth2:std_logic_vector(3 downto 0);
signal setm1:std_logic_vector(3 downto 0);
signal setm2:std_logic_vector(3 downto 0);
signal sec1:std_logic_vector(3 downto 0);
signal sec2:std_logic_vector(3 downto 0);
signal h1:std_logic_vector(3 downto 0);
signal h2:std_logic_vector(3 downto 0);
signal m1:std_logic_vector(3 downto 0);
signal m2:std_logic_vector(3 downto 0);
signal s1:std_logic_vector(3 downto 0);
signal s2:std_logic_vector(3 downto 0);
signal Q:std_logic_vector(5 downto 0);
SIGNAL CLK1MHZ,CLK1khz,clk: STD_LOGIC;
SIGNAL Q1:std_logic_vector(9 downto 0);
SIGNAL Q2:std_logic_vector(9 downto 0);
begin
-------------------------------------------------把40MHZ的频率转变成分别为1KHZ和1HZ的频率
PROCESS(CLK0)
BEGIN
IF(CLK0'EVENT AND CLK0='1')THEN
IF(Q="100111")THEN
Q<="000000";
CLK1MHZ<='1';
ELSE
Q<=Q+1;
CLK1MHZ<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK1MHZ) IS
BEGIN
IF(CLK1MHZ'EVENT AND CLK1MHZ='1')THEN
IF(Q1="1111111111")THEN
Q1<="0000000000";
CLK1KHZ<='0';
ELSIF(Q1<="0111111111")THEN
CLK1KHZ<='0';
Q1<=Q1+1;
ELSE
Q1<=Q1+1;
CLK1KHZ<='1';
END IF;
END IF;
END PROCESS;
PROCESS(CLK1kHZ) IS
BEGIN
IF(CLK1kHZ'EVENT AND CLK1kHZ='1')THEN
IF(Q2="1111111111")THEN
Q2<="0000000000";
CLK<='0';
ELSIF(Q2<="0111111111")THEN
CLK<='0';
Q2<=Q2+1;
ELSE
Q2<=Q2+1;
CLK<='1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------
h110:process(clk,hou2,min1,min2,sec1,sec2,md1,md2)
begin
if clk'event and clk='1' then
if (hou1="0010" and hou2="0011")and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001") then
hou1<="0000";
elsif hou1="0010"and hou2="0011"and md1='0' and md2="01" then--
hou1<="0000";
elsif (hou2="1001"and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001"))or (hou2="1001"and md1='0' and md2="01") then
hou1<=hou1+1;
end if;
end if;
end process h110;
--------------------------------------------
h220:process(clk,min1,min2,sec1,sec2,md1,md2,hou1)
begin
if clk'event and clk='1' then
if (hou1="0010" and hou2="0011")and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001") then
hou2<="0000";
elsif hou2="1001"and(min1="0101" and min2="1001") and (sec1="0101" and sec2="1001") then
hou2<="0000";
elsif ((hou2="1001"and md1='0' and md2="01") or (hou1="0010" and hou2="0011" and md1='0' and md2="01")) then
hou2<="0000";--md<='1';
elsif ((min1="0101" and min2="1001") and (sec1="0101" and sec2="1001"))or (md1='0' and md2="01") then
hou2<=hou2+1;--speak<=clk;
end if;
end if;
end process h220;
-----------------------------------------------
m110:process(clk,min2,sec1,sec2,md1,md2)
begin
if clk'event and clk='1' then
if (min1="0101" and min2="1001") and (sec1="0101" and sec2="1001") then
min1<="0000";
elsif min1="0101"and min2="1001"and (md1='0' and md2="10")then
min1<="0000";
elsif (min2="1001"and (sec1="0101" and sec2="1001"))or(min2="1001"and md1='0' and md2="10") then
min1<=min1+1;
end if;
end if;--end if;
end process m110;
-----------------------------------
m220:process(clk,sec1,sec2,md1,md2)
begin
if clk'event and clk='1' then
if min2="1001"and sec1="0101" and sec2="1001" then
min2<="0000";
else if(min2="1001"and md1='0' and md2="10")then
min2<="0000";
elsif (sec1="0101" and sec2="1001")or(md1='0' and md2="10")then
min2<=min2+1;
end if;
end if;end if;
end process m220;
---------------------------------------------
s110:process(clk)
begin
if clk'event and clk='1' then
if (sec1="0101" and sec2="1001")then
sec1<="0000";
else if sec2="1001"then
sec1<=sec1+1;
end if;
end if;end if;
end process s110;
--------------------------------------------
s220:process(clk)
begin
if clk'event and clk='1' then
if sec2="1001" then
sec2<="0000";
else sec2<=sec2+1;
end if;
end if;
end process s220;
------------------------------------------
sethour1:process(clk,seth2)
begin
if clk'event and clk='1' then
if seth1="0010"and seth2="0011" then
seth1<="0000";
elsif seth2="1001" then
seth1<=seth1+1;
end if;
end if;
end process sethour1;
-------------------------------------------
sethour2:process(clk,md1,md2,seth1)
begin
if clk'event and clk='1' then
if (seth1="0010"and seth2="0011")or seth2="1001"then
seth2<="0000";
elsif md1='1' and md2="00" then
seth2<=seth2+1;
end if;
end if;
end process sethour2;
----------------------------------------
setmin1:process(clk,setm2)
begin
if clk'event and clk='1' then
if setm1="0101"and setm2="1001"then
setm1<="0000";
elsif setm2="1001"then
setm1<=setm1+1;
end if;
end if;
end process setmin1;
----------------------------------------------
setmin2:process(clk,md1,md2)
begin
if clk'event and clk='1'then
if setm2="1001"then
setm2<="0000";
elsif md1='1' and md2="01"then
setm2<=setm2+1;
end if;
end if;
end process setmin2;
--------------------------------------------
--------------------------------------------
speaker:process(clk1khz,hou1,hou2,min1,min2)
begin
if clk1khz'event and clk1khz='1'then
if seth1=hou1 and seth2=hou2 and setm1=min1 and setm2=min2 then
speak<=clk1khz;
else speak<='0';
end if;
end if;
end process speaker;
-------------------------------------------
-------------------------------------------
disp:process(clk1khz,sel,md1,hou1,hou2,min1,min2,sec1,sec2,seth1,seth2,setm1,setm2)
begin
if rising_edge(clk1khz)then
if sel="000" then
selout<="100000";
sel<="001";
case h1 is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when others =>dout<="1000000";
end case;
elsif sel="001" then
selout<="010000";
sel<="010";
case h2 is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when "0110"=>dout<="1111101";
when "0111"=>dout<="0000111";
when "1000"=>dout<="1111111";
when "1001"=>dout<="1101111";
when others=>dout<="1000000";
end case;
elsif sel="010" then
sel<="011";
selout<="001000";
case m1 is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when others=>dout<="1000000";
end case;
elsif sel="011" then
sel<="100";
selout<="000100";
case m2 is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when "0110"=>dout<="1111101";
when "0111"=>dout<="0000111";
when "1000"=>dout<="1111111";
when "1001"=>dout<="1101111";
when others=>dout<="1000000";
end case;
elsif sel="100" then
selout<="000010";
sel<="101";
case s1 is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when others=>dout<="1000000";
end case;
elsif sel="101" then
sel<="000";
selout<="000001";
case s2 is
when "0000"=>dout<="0111111";
when "0001"=>dout<="0000110";
when "0010"=>dout<="1011011";
when "0011"=>dout<="1001111";
when "0100"=>dout<="1100110";
when "0101"=>dout<="1101101";
when "0110"=>dout<="1111101";
when "0111"=>dout<="0000111";
when "1000"=>dout<="1111111";
when "1001"=>dout<="1101111";
when others=>dout<="1000000";
end case;
end if;
if md1='0' then---------------
h1<=hou1;h2<=hou2;
m1<=min1;m2<=min2;
s1<=sec1;s2<=sec2;
else -----------
h1<=seth1;h2<=seth2;
m1<=setm1;m2<=setm2;
s1<="1111";s2<="1111";
end if;
end if;
end process disp;
------------------------------------------
end one;
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