uart_transmitter.v

来自「verilog描述的uart发射端功能实现」· Verilog 代码 · 共 107 行

module  uart_transmitter(
						Serial_out,                     //总线输出
						Data_Bus,						//总线输入数据
						Byte_ready,						//
						Load_XMT_datareg,
						T_byte,
						clk,
						Rst_n	
						);
input clk;
input Rst_n;
input T_byte;
input Byte_ready;
input [7:0]	Data_Bus;
input Load_XMT_datareg;

output Serial_out;                    //串行输出到数据通道

parameter 
		Idel = 3'd1,
		waiting = 3'd2,
		sending = 3'd3;
parameter all_ones = 9'b1_1111_1111;

reg [7:0]	XMT_datareg;
reg [8:0]	XMT_shftreg;
reg 		Load_XMT_shftreg;
reg [2:0]	state,next_state;
reg [3:0]	bit_count;
reg			clear;
reg			start;
reg			shift;

assign Serial_out = XMT_shftreg[0];

always @ (posedge clk)
	if(!Rst_n)
		state <= Idel;
	else
		state <= next_state;
		
always @ (state or T_byte or Byte_ready  or bit_count) //凡是读到了的信号
	begin
			Load_XMT_shftreg = 1'b0;
			shift = 1'b0;
			clear = 1'b0;
			start = 1'b0;
			next_state = state ;
			case(state)
				Idel:
					if(Byte_ready == 1'b1)
					begin
							Load_XMT_shftreg = 1'b1;
							next_state = waiting;
					end	
				waiting:
					begin
						if(T_byte==1'b1)
							begin
								start = 1'b1;
								next_state = sending;
							end
						else
							next_state = waiting;
					end
				sending:
					begin
						if(bit_count == 4'd9)
							begin
								clear = 1'b1;
								next_state = Idel;
							end
						else
							begin
								shift =  1'b1;
								next_state = sending;
							end
					end
				default:
					next_state = Idel;
				endcase
	end
	
always @ (posedge clk or negedge Rst_n)
	if(!Rst_n)
		begin
			XMT_shftreg <= all_ones;
			bit_count <= 4'd0;
		end 
	else
		begin
			if(Load_XMT_datareg)
				XMT_datareg <= Data_Bus;
			if(Load_XMT_shftreg)
				XMT_shftreg <= {XMT_datareg, 1'b1};
			if(start)
				XMT_shftreg[0] <= 1'b0;
			if(clear)
				bit_count <= 4'd0;
			else if(shift)
				bit_count <= bit_count + 1'b1;
			if(shift)
				XMT_shftreg <= {1'b1, XMT_shftreg[8:1]};
				
		end
	
endmodule