invmod.v

verilog实现的1024位的大数模逆算法

					temp_rdaddr <= uvBD_addr;
					uvBD_addr <= uvBD_addr + 1'b1;
					temp_reg <= ~InvMod_q;                  //get Bi
					temp_reg1 <= temp_reg2[33:32];
					cnt <= cnt + 1'b1;
					cs <= B_minus_m_s1;
     			end
			 B_minus_div_s0:
				begin
					temp_rden <= 1'b1;
					temp_wren <= 1'b1;
					cnt <= 5'd0;
					temp_wraddr <= temp_addr;
					temp_data <=  temp_reg + temp_reg1 + InvMod_q;
					temp_rdaddr <= uvBD_addr;          //read B1
					uvBD_addr <= uvBD_addr + 1'b1;
					cs <= B_minus_div_s1;		
				end		
			B_minus_div_s1:
				begin		
					temp_wren <= 1'b0;
					temp_rden <= 1'b1;
					temp_rdaddr <= uvBD_addr; //read_B1
					uvBD_addr <= uvBD_addr + 1'b1;
					temp_reg[30:0] <= InvMod_q[31:1];
					cs <= B_div_1;
				end

	
			// 第二部分  判断v 
			read_v0:                                             
				begin
					temp_rden <= 1'b1;
					temp_wren <= 1'b0;
					temp_rdaddr <=`v_base_addr;
					uvBD_addr <= `v_base_addr + 1'b1;
					cs <= read_v1;		
				end	
			read_v1:
				begin
					temp_rdaddr <= uvBD_addr;
					uvBD_addr <= uvBD_addr + 1'b1;
					cs <= Judge_v0;
				end
			Judge_v0:
				begin
					temp_reg[30:0] <= InvMod_q[31:1];
					temp_rdaddr <= uvBD_addr;
					uvBD_addr <= uvBD_addr + 1'b1;
					if(InvMod_q[0]==0)
						cs <= Div_v_1;
					else
						cs <= Judge_u_v_s0;						
				end
			Div_v_1:
				begin
					temp_rden <= 1'b1;
					temp_wren <= 1'b1;
					temp_rdaddr <= uvBD_addr;
					temp_wraddr <= uvBD_addr - 2'd3;
					uvBD_addr <= uvBD_addr + 1'b1;
					temp_data <= {InvMod_q[0],temp_reg[30:0]};
					temp_reg [30:0] <= InvMod_q[31:1];
					cnt <= cnt + 1'b1;
					if(cnt==5'd30)
						cs <= Div_v_0;
					else
						cs <= Div_v_1;
				end
			Div_v_0:                        
				begin
					temp_rden <= 1'b1;
					temp_wren <= 1'b1;
					temp_rdaddr <= InvMod_D_addr;   //read B0
					temp_wraddr <= uvBD_addr - 2'd3;
					uvBD_addr <= InvMod_D_addr + 1'b1;
					temp_data <= {temp_reg[30],temp_reg[30:0]};
					cs <= read_D0;
				end
			read_D0:                         //start from here
				begin
				if(InvMod_q[0]==1'b0)
					begin
					cnt <= 1'b0;
					temp_wren <= 1'b0;
					temp_rden <= 1'b1;
					temp_rdaddr <= uvBD_addr; //read_D1
					uvBD_addr <= uvBD_addr + 1'b1;
					//temp_reg[30:0] <= InvMod_q[31:1];
						cs <= D_div_2;
					end
				else
					begin
						temp_wren <= 1'b0;
						temp_rden <= 1'b1;
						temp_rdaddr <= InvMod_a_addr;
						a_addr <= InvMod_a_addr + 1'b1;
						cs <= D_minus_a_s0;
					end
				end
			D_div_2:
				begin
					temp_wren <= 1'b0;
					temp_rden <= 1'b1;
					temp_rdaddr <= uvBD_addr; //read_B1
					uvBD_addr <= uvBD_addr + 1'b1;
					temp_reg[30:0] <= InvMod_q[31:1];
					cs <= D_div_1;
				end
			D_div_1:
				begin
					temp_rden <= 1'b1;
					temp_wren <= 1'b1;
					temp_rdaddr <= uvBD_addr;
					uvBD_addr <= uvBD_addr + 1'b1;
					temp_wraddr <= uvBD_addr - 2'd3;
					temp_data <= {InvMod_q[0],temp_reg[30:0]};
					temp_reg[30:0] <= InvMod_q[31:1];
					cnt <= cnt + 1'b1;
					if(cnt == 5'd28)
						cs <= D_div_0;
					else
						cs <= D_div_1;
				end
			D_div_0:
				begin
					temp_rden <= 1'b0;
					temp_wren <= 1'b1;
					temp_data <= {temp_reg[30],temp_reg[30:0]};
					temp_wraddr <= uvBD_addr - 2'd3;
					uvBD_addr <= uvBD_addr + 1'b1;
					cnt <= cnt + 1'b1;
					if(cnt == 5'd31)
						cs <= read_v0;
					else
						cs <= D_div_0;
					
				end
			D_minus_a_s0:
				begin
						uvBD_addr <= InvMod_D_addr + 1'b1;
						temp_rden <= 1'b1;
						temp_wren <= 1'b0;
						temp_rdaddr <= InvMod_D_addr;
						temp_reg1 <= 2'd1;                //read D0
						temp_addr <= InvMod_D_addr;
						cnt <= 5'd0;
						cs <= D_minus_a_s1;
				end
			D_minus_a_s1:
				begin
					temp_rden <= 1'b0;
					temp_wren <= 1'b0;	
					temp_reg <= ~InvMod_q;			
					cs <=  D_minus_a_s2;
				end
			D_minus_a_s2:
				begin
					if(cnt == 5'd31)
						begin
							temp_rden <= 1'b1;
							temp_rdaddr <= InvMod_D_addr;
							uvBD_addr <= InvMod_D_addr + 1'b1; //read D0				
							cs <= D_minus_div_s0;
						end
					else
						begin
							temp_rden <= 1'b1;		
							temp_wren <= 1'b1;       
							temp_reg2 <=  temp_reg + temp_reg1 + InvMod_q;    //write get D0
							temp_data <=  temp_reg + temp_reg1 + InvMod_q;
							temp_rdaddr <= a_addr;
							a_addr <= a_addr + 1'b1;
							temp_wraddr <= temp_addr;
							temp_addr <= temp_addr + 1'b1;         //read ai
							cs <= D_minus_a_s3;
						end
				end
			D_minus_a_s3:
				begin	
					temp_rden <= 1'b1;
					temp_wren <= 1'b0;
					temp_rdaddr <= uvBD_addr;
					uvBD_addr <= uvBD_addr + 1'b1;
					temp_reg <= ~InvMod_q;                  //get Bi
					temp_reg1 <= temp_reg2[33:32];
					cnt <= cnt + 1'b1;
					cs <= D_minus_a_s1;
     			end
			 D_minus_div_s0:
				begin
					temp_rden <= 1'b1;
					temp_wren <= 1'b1;
					cnt <= 5'd0;
					temp_wraddr <= temp_addr;
					temp_data <=  temp_reg + temp_reg1 + InvMod_q;
					temp_rdaddr <= uvBD_addr;          //read B1
					uvBD_addr <= uvBD_addr + 1'b1;
					cs <= D_minus_div_s1;		
				end		
			D_minus_div_s1:
				begin		
					temp_wren <= 1'b0;
					temp_rden <= 1'b1;
					temp_rdaddr <= uvBD_addr; //read_B1
					uvBD_addr <= uvBD_addr + 1'b1;
					temp_reg[30:0] <= InvMod_q[31:1];
					cs <= D_div_1;
				end
	
	/*
		第三部分 判断u和v的大小 
		reg  [31:0]	temp_reg;
		reg  [1:0]  temp_reg1;
		reg  [33:0] temp_reg2;
	*/
		Judge_u_v_s0:		//read u[31]
					begin		
						temp_wren <= 1'b0;
						cnt <= 5'd31;
						uvBD_addr <= `u_base_addr + 5'd30;  //the address of u
						a_addr <= `v_base_addr + 5'd31 ;     //the address of v
						temp_rden <= 1'b1;
						temp_rdaddr <= `u_base_addr + 5'd31;
						cs <= Judge_u_v_s1;
					end
				Judge_u_v_s1:  //read v[31]
					begin
						temp_rdaddr <= a_addr;
						a_addr <= a_addr - 1'b1;
						temp_rden <= 1'b1;
						cs <= Judge_u_v_s2;
					end
				Judge_u_v_s2://get ui;  
					begin
						temp_rden <= 1'b0;
						//temp_reg[31:0] <= InvMod_q;
						temp_reg2 <= {2'b0,InvMod_q};
						cs <= Judge_u_v_s3;
					end
				Judge_u_v_s3:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= uvBD_addr; 	//read  u[30]
						uvBD_addr <= uvBD_addr - 1'b1;
						{temp_reg1,temp_reg} <= temp_reg2 - InvMod_q;
						cs <= Judge_u_v_s4;
					end
				Judge_u_v_s4:
					begin
						temp_rden <= 1'b1;	//read v[30]
						temp_rdaddr <= a_addr;
						a_addr <= a_addr - 1'b1;
						cnt <= cnt -1'd1;
						if(temp_reg1[0]==1'b1)
							cs <= v_minus_u;
						else 
							begin
								if(temp_reg==32'b0)
								begin
									if(cnt==5'd0)
										cs <= u_minus_v;          //u ==  v
									else
										cs <= Judge_u_v_s2;
								end
								else cs <= u_minus_v;
							end
					end
				v_minus_u:
					begin
						uvBD_addr <= `v_base_addr;   //the addr of v
						a_addr <= `u_base_addr;  // the addr of u
						m_addr <= InvMod_D_addr; // the addr of D
						temp_addr <= `B_base_addr; //the addr of B
						temp_rden <= 1'b0;
						temp_wren <= 1'b0;
						cs <= minus_uv_s0;
					end
				u_minus_v:
					begin
						uvBD_addr <= `u_base_addr;   //the addr of u
						a_addr <= `v_base_addr;  // the addr of v
						m_addr <= `B_base_addr; // the addr of B
						temp_addr <= InvMod_D_addr; //the addr of D
						temp_rden <= 1'b0;
						temp_wren <= 1'b0;
						cs <= minus_uv_s0;
					end
				minus_uv_s0:
					begin
						temp_rden <= 1'b1;
						temp_wren <= 1'b0;
						temp_rdaddr <= a_addr;
						a_addr <= a_addr + 1'b1;
						temp_reg1 <= 2'd1;
						cnt <= 5'd0;
						cs <= minus_uv_s1;
					end
				minus_uv_s1:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= uvBD_addr;
						cs <= minus_uv_s2;
					end
				minus_uv_s2:
					begin
						temp_wren <= 1'b0;
						temp_rden <= 1'b0;
						temp_reg <= ~InvMod_q;
						cs <= minus_uv_s3;
					end
				minus_uv_s3:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= a_addr;
						a_addr <= a_addr + 1'b1;
						temp_reg2 <= temp_reg + temp_reg1 + InvMod_q;
						cs <= minus_uv_s4;
					end
				minus_uv_s4:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= uvBD_addr + 1'b1;
						temp_wren <= 1'b1;
						temp_wraddr <= uvBD_addr;
						temp_data <= temp_reg2[31:0];
						temp_reg1 <= temp_reg2[33:32];
						uvBD_addr <= uvBD_addr + 1'b1;
						cnt <= cnt + 1'b1;
						if(cnt == 5'b1_1111)
							cs <= minus_BD_s0;
						else cs <= minus_uv_s2;
					end
				minus_BD_s0:
					begin
						cnt <= 5'd0;
						temp_rden <= 1'b1;
						temp_rdaddr <= temp_addr;
						temp_addr <= temp_addr + 1'b1;
						temp_reg1 <= 2'd1;
						cs <= minus_BD_s1;
					end
				minus_BD_s1:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= m_addr;
						cs <= minus_BD_s2;
					end
				minus_BD_s2:
					begin
						temp_wren <= 1'b0;
						temp_rden <= 1'b0;
						temp_reg <= ~InvMod_q;
						cs <= minus_BD_s3;
					end
				minus_BD_s3:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= temp_addr;
						temp_addr <= temp_addr + 1'b1;
						temp_reg2 <= temp_reg + temp_reg1 + InvMod_q;
						cs <= minus_BD_s4;
					end
				minus_BD_s4:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= m_addr + 1'b1;
						temp_wren <= 1'b1;
						temp_wraddr <= m_addr;
						temp_data <= temp_reg2[31:0];
						temp_reg1 <= temp_reg2[33:32];
						m_addr <= m_addr + 1'b1;
						cnt <= cnt + 1'b1;
						if(cnt == 5'b1_1111)
							cs <= Get_Result;
						else cs <= minus_BD_s2;
					end
				Get_Result:
					begin
						temp_rden <= 1'b1;         //read u[31]
						temp_wren <= 1'b0;
						cnt <= 5'd31;
						temp_rdaddr <= `u_base_addr + 5'd31;
						m_addr <= `u_base_addr + 5'd30;
						cs <= Judge_u0_0;
					end
				Judge_u0_0:
					begin
						temp_rden <= 1'b1;
						temp_rdaddr <= m_addr;
						m_addr <= m_addr - 1'b1;
						cs <= Judge_u0_1;
						cnt <= cnt - 1'b1;
					end
				Judge_u0_1:
					begin
						if(InvMod_q != 32'd0)
							cs <= read_u0;
						else
							if(cnt == 32'd0)
							begin
								temp_rden <= 1'b0;
								cs <= Judge_u0_2; 
							end
							else
								begin
								temp_rden <= 1'b1;
								temp_rdaddr <= m_addr;
								m_addr <= m_addr - 1'b1;
								cnt <= cnt - 1'b1;
								cs <= Judge_u0_0; 
								end
					end
				Judge_u0_2:
					begin
						if(InvMod_q == 32'd0)
							cs <= done;
						else
							cs <= read_u0;
					end
			/*Judge_u0_3:
					begin
						if(InvMod_q == 32'd0)
							cs <= done;
						else
							cs <= read_u0;
					end
			*/
			done:
				begin
					temp_rden <= 1'b0;
					temp_wren <= 1'b0;
					InvMod_done <= 1'b1;
					InvMod_valid <= 1'b0;
					cs <= done;
				end
			endcase
	endmodule