📄 segment1.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node \"Clk\" is an undefined clock" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register Cout\[1\] register Cout\[28\] 208.25 MHz 4.802 ns Internal " "Info: Clock \"Clk\" has Internal fmax of 208.25 MHz between source register \"Cout\[1\]\" and destination register \"Cout\[28\]\" (period= 4.802 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.522 ns + Longest register register " "Info: + Longest register to register delay is 4.522 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Cout\[1\] 1 REG LCFF_X14_Y14_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y14_N5; Fanout = 2; REG Node = 'Cout\[1\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Cout[1] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.754 ns) + CELL(0.621 ns) 1.375 ns Cout\[1\]~176 2 COMB LCCOMB_X14_Y14_N4 2 " "Info: 2: + IC(0.754 ns) + CELL(0.621 ns) = 1.375 ns; Loc. = LCCOMB_X14_Y14_N4; Fanout = 2; COMB Node = 'Cout\[1\]~176'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.375 ns" { Cout[1] Cout[1]~176 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.461 ns Cout\[2\]~178 3 COMB LCCOMB_X14_Y14_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.461 ns; Loc. = LCCOMB_X14_Y14_N6; Fanout = 2; COMB Node = 'Cout\[2\]~178'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[1]~176 Cout[2]~178 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.547 ns Cout\[3\]~180 4 COMB LCCOMB_X14_Y14_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.547 ns; Loc. = LCCOMB_X14_Y14_N8; Fanout = 2; COMB Node = 'Cout\[3\]~180'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[2]~178 Cout[3]~180 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.633 ns Cout\[4\]~182 5 COMB LCCOMB_X14_Y14_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.633 ns; Loc. = LCCOMB_X14_Y14_N10; Fanout = 2; COMB Node = 'Cout\[4\]~182'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[3]~180 Cout[4]~182 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.719 ns Cout\[5\]~184 6 COMB LCCOMB_X14_Y14_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.719 ns; Loc. = LCCOMB_X14_Y14_N12; Fanout = 2; COMB Node = 'Cout\[5\]~184'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[4]~182 Cout[5]~184 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.909 ns Cout\[6\]~186 7 COMB LCCOMB_X14_Y14_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.190 ns) = 1.909 ns; Loc. = LCCOMB_X14_Y14_N14; Fanout = 2; COMB Node = 'Cout\[6\]~186'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Cout[5]~184 Cout[6]~186 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.995 ns Cout\[7\]~188 8 COMB LCCOMB_X14_Y14_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.995 ns; Loc. = LCCOMB_X14_Y14_N16; Fanout = 2; COMB Node = 'Cout\[7\]~188'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[6]~186 Cout[7]~188 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.081 ns Cout\[8\]~190 9 COMB LCCOMB_X14_Y14_N18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.081 ns; Loc. = LCCOMB_X14_Y14_N18; Fanout = 2; COMB Node = 'Cout\[8\]~190'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[7]~188 Cout[8]~190 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.167 ns Cout\[9\]~192 10 COMB LCCOMB_X14_Y14_N20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.167 ns; Loc. = LCCOMB_X14_Y14_N20; Fanout = 2; COMB Node = 'Cout\[9\]~192'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[8]~190 Cout[9]~192 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.253 ns Cout\[10\]~194 11 COMB LCCOMB_X14_Y14_N22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.253 ns; Loc. = LCCOMB_X14_Y14_N22; Fanout = 2; COMB Node = 'Cout\[10\]~194'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[9]~192 Cout[10]~194 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.339 ns Cout\[11\]~196 12 COMB LCCOMB_X14_Y14_N24 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.339 ns; Loc. = LCCOMB_X14_Y14_N24; Fanout = 2; COMB Node = 'Cout\[11\]~196'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[10]~194 Cout[11]~196 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.425 ns Cout\[12\]~198 13 COMB LCCOMB_X14_Y14_N26 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.425 ns; Loc. = LCCOMB_X14_Y14_N26; Fanout = 2; COMB Node = 'Cout\[12\]~198'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[11]~196 Cout[12]~198 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.511 ns Cout\[13\]~200 14 COMB LCCOMB_X14_Y14_N28 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.511 ns; Loc. = LCCOMB_X14_Y14_N28; Fanout = 2; COMB Node = 'Cout\[13\]~200'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[12]~198 Cout[13]~200 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.686 ns Cout\[14\]~202 15 COMB LCCOMB_X14_Y14_N30 2 " "Info: 15: + IC(0.000 ns) + CELL(0.175 ns) = 2.686 ns; Loc. = LCCOMB_X14_Y14_N30; Fanout = 2; COMB Node = 'Cout\[14\]~202'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { Cout[13]~200 Cout[14]~202 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.772 ns Cout\[15\]~204 16 COMB LCCOMB_X14_Y13_N0 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.772 ns; Loc. = LCCOMB_X14_Y13_N0; Fanout = 2; COMB Node = 'Cout\[15\]~204'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[14]~202 Cout[15]~204 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.858 ns Cout\[16\]~206 17 COMB LCCOMB_X14_Y13_N2 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.858 ns; Loc. = LCCOMB_X14_Y13_N2; Fanout = 2; COMB Node = 'Cout\[16\]~206'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[15]~204 Cout[16]~206 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.944 ns Cout\[17\]~208 18 COMB LCCOMB_X14_Y13_N4 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.944 ns; Loc. = LCCOMB_X14_Y13_N4; Fanout = 2; COMB Node = 'Cout\[17\]~208'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[16]~206 Cout[17]~208 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.030 ns Cout\[18\]~210 19 COMB LCCOMB_X14_Y13_N6 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.030 ns; Loc. = LCCOMB_X14_Y13_N6; Fanout = 2; COMB Node = 'Cout\[18\]~210'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[17]~208 Cout[18]~210 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.116 ns Cout\[19\]~212 20 COMB LCCOMB_X14_Y13_N8 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.116 ns; Loc. = LCCOMB_X14_Y13_N8; Fanout = 2; COMB Node = 'Cout\[19\]~212'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[18]~210 Cout[19]~212 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.202 ns Cout\[20\]~214 21 COMB LCCOMB_X14_Y13_N10 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.202 ns; Loc. = LCCOMB_X14_Y13_N10; Fanout = 2; COMB Node = 'Cout\[20\]~214'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[19]~212 Cout[20]~214 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.288 ns Cout\[21\]~216 22 COMB LCCOMB_X14_Y13_N12 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.288 ns; Loc. = LCCOMB_X14_Y13_N12; Fanout = 2; COMB Node = 'Cout\[21\]~216'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[20]~214 Cout[21]~216 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.478 ns Cout\[22\]~218 23 COMB LCCOMB_X14_Y13_N14 2 " "Info: 23: + IC(0.000 ns) + CELL(0.190 ns) = 3.478 ns; Loc. = LCCOMB_X14_Y13_N14; Fanout = 2; COMB Node = 'Cout\[22\]~218'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Cout[21]~216 Cout[22]~218 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.564 ns Cout\[23\]~220 24 COMB LCCOMB_X14_Y13_N16 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.564 ns; Loc. = LCCOMB_X14_Y13_N16; Fanout = 2; COMB Node = 'Cout\[23\]~220'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[22]~218 Cout[23]~220 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.650 ns Cout\[24\]~222 25 COMB LCCOMB_X14_Y13_N18 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.650 ns; Loc. = LCCOMB_X14_Y13_N18; Fanout = 2; COMB Node = 'Cout\[24\]~222'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[23]~220 Cout[24]~222 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.736 ns Cout\[25\]~224 26 COMB LCCOMB_X14_Y13_N20 2 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.736 ns; Loc. = LCCOMB_X14_Y13_N20; Fanout = 2; COMB Node = 'Cout\[25\]~224'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[24]~222 Cout[25]~224 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.822 ns Cout\[26\]~226 27 COMB LCCOMB_X14_Y13_N22 2 " "Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.822 ns; Loc. = LCCOMB_X14_Y13_N22; Fanout = 2; COMB Node = 'Cout\[26\]~226'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[25]~224 Cout[26]~226 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.908 ns Cout\[27\]~228 28 COMB LCCOMB_X14_Y13_N24 1 " "Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.908 ns; Loc. = LCCOMB_X14_Y13_N24; Fanout = 1; COMB Node = 'Cout\[27\]~228'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Cout[26]~226 Cout[27]~228 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.414 ns Cout\[28\]~229 29 COMB LCCOMB_X14_Y13_N26 1 " "Info: 29: + IC(0.000 ns) + CELL(0.506 ns) = 4.414 ns; Loc. = LCCOMB_X14_Y13_N26; Fanout = 1; COMB Node = 'Cout\[28\]~229'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Cout[27]~228 Cout[28]~229 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.522 ns Cout\[28\] 30 REG LCFF_X14_Y13_N27 2 " "Info: 30: + IC(0.000 ns) + CELL(0.108 ns) = 4.522 ns; Loc. = LCFF_X14_Y13_N27; Fanout = 2; REG Node = 'Cout\[28\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { Cout[28]~229 Cout[28] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.768 ns ( 83.33 % ) " "Info: Total cell delay = 3.768 ns ( 83.33 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.754 ns ( 16.67 % ) " "Info: Total interconnect delay = 0.754 ns ( 16.67 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.522 ns" { Cout[1] Cout[1]~176 Cout[2]~178 Cout[3]~180 Cout[4]~182 Cout[5]~184 Cout[6]~186 Cout[7]~188 Cout[8]~190 Cout[9]~192 Cout[10]~194 Cout[11]~196 Cout[12]~198 Cout[13]~200 Cout[14]~202 Cout[15]~204 Cout[16]~206 Cout[17]~208 Cout[18]~210 Cout[19]~212 Cout[20]~214 Cout[21]~216 Cout[22]~218 Cout[23]~220 Cout[24]~222 Cout[25]~224 Cout[26]~226 Cout[27]~228 Cout[28]~229 Cout[28] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.522 ns" { Cout[1] {} Cout[1]~176 {} Cout[2]~178 {} Cout[3]~180 {} Cout[4]~182 {} Cout[5]~184 {} Cout[6]~186 {} Cout[7]~188 {} Cout[8]~190 {} Cout[9]~192 {} Cout[10]~194 {} Cout[11]~196 {} Cout[12]~198 {} Cout[13]~200 {} Cout[14]~202 {} Cout[15]~204 {} Cout[16]~206 {} Cout[17]~208 {} Cout[18]~210 {} Cout[19]~212 {} Cout[20]~214 {} Cout[21]~216 {} Cout[22]~218 {} Cout[23]~220 {} Cout[24]~222 {} Cout[25]~224 {} Cout[26]~226 {} Cout[27]~228 {} Cout[28]~229 {} Cout[28] {} } { 0.000ns 0.754ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.016 ns - Smallest " "Info: - Smallest clock skew is -0.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 2.855 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk\" to destination register is 2.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.910 ns) + CELL(0.666 ns) 2.855 ns Cout\[28\] 3 REG LCFF_X14_Y13_N27 2 " "Info: 3: + IC(0.910 ns) + CELL(0.666 ns) = 2.855 ns; Loc. = LCFF_X14_Y13_N27; Fanout = 2; REG Node = 'Cout\[28\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { Clk~clkctrl Cout[28] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.26 % ) " "Info: Total cell delay = 1.806 ns ( 63.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.049 ns ( 36.74 % ) " "Info: Total interconnect delay = 1.049 ns ( 36.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { Clk Clk~clkctrl Cout[28] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[28] {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.871 ns - Longest register " "Info: - Longest clock path from clock \"Clk\" to source register is 2.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.926 ns) + CELL(0.666 ns) 2.871 ns Cout\[1\] 3 REG LCFF_X14_Y14_N5 2 " "Info: 3: + IC(0.926 ns) + CELL(0.666 ns) = 2.871 ns; Loc. = LCFF_X14_Y14_N5; Fanout = 2; REG Node = 'Cout\[1\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.592 ns" { Clk~clkctrl Cout[1] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 62.90 % ) " "Info: Total cell delay = 1.806 ns ( 62.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns ( 37.10 % ) " "Info: Total interconnect delay = 1.065 ns ( 37.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { Clk Clk~clkctrl Cout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[1] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { Clk Clk~clkctrl Cout[28] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[28] {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { Clk Clk~clkctrl Cout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[1] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 19 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.522 ns" { Cout[1] Cout[1]~176 Cout[2]~178 Cout[3]~180 Cout[4]~182 Cout[5]~184 Cout[6]~186 Cout[7]~188 Cout[8]~190 Cout[9]~192 Cout[10]~194 Cout[11]~196 Cout[12]~198 Cout[13]~200 Cout[14]~202 Cout[15]~204 Cout[16]~206 Cout[17]~208 Cout[18]~210 Cout[19]~212 Cout[20]~214 Cout[21]~216 Cout[22]~218 Cout[23]~220 Cout[24]~222 Cout[25]~224 Cout[26]~226 Cout[27]~228 Cout[28]~229 Cout[28] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.522 ns" { Cout[1] {} Cout[1]~176 {} Cout[2]~178 {} Cout[3]~180 {} Cout[4]~182 {} Cout[5]~184 {} Cout[6]~186 {} Cout[7]~188 {} Cout[8]~190 {} Cout[9]~192 {} Cout[10]~194 {} Cout[11]~196 {} Cout[12]~198 {} Cout[13]~200 {} Cout[14]~202 {} Cout[15]~204 {} Cout[16]~206 {} Cout[17]~208 {} Cout[18]~210 {} Cout[19]~212 {} Cout[20]~214 {} Cout[21]~216 {} Cout[22]~218 {} Cout[23]~220 {} Cout[24]~222 {} Cout[25]~224 {} Cout[26]~226 {} Cout[27]~228 {} Cout[28]~229 {} Cout[28] {} } { 0.000ns 0.754ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { Clk Clk~clkctrl Cout[28] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.855 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[28] {} } { 0.000ns 0.000ns 0.139ns 0.910ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.871 ns" { Clk Clk~clkctrl Cout[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.871 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Cout[1] {} } { 0.000ns 0.000ns 0.139ns 0.926ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk Sev_Seg_Led_Data_n\[4\] Sev_Seg_Led_Data_n\[4\]~reg0 8.544 ns register " "Info: tco from clock \"Clk\" to destination pin \"Sev_Seg_Led_Data_n\[4\]\" through register \"Sev_Seg_Led_Data_n\[4\]~reg0\" is 8.544 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 2.850 ns + Longest register " "Info: + Longest clock path from clock \"Clk\" to source register is 2.850 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns Clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'Clk'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Clk } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns Clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'Clk~clkctrl'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { Clk Clk~clkctrl } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.905 ns) + CELL(0.666 ns) 2.850 ns Sev_Seg_Led_Data_n\[4\]~reg0 3 REG LCFF_X10_Y13_N1 1 " "Info: 3: + IC(0.905 ns) + CELL(0.666 ns) = 2.850 ns; Loc. = LCFF_X10_Y13_N1; Fanout = 1; REG Node = 'Sev_Seg_Led_Data_n\[4\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { Clk~clkctrl Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.37 % ) " "Info: Total cell delay = 1.806 ns ( 63.37 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.044 ns ( 36.63 % ) " "Info: Total interconnect delay = 1.044 ns ( 36.63 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { Clk Clk~clkctrl Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Sev_Seg_Led_Data_n[4]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.390 ns + Longest register pin " "Info: + Longest register to pin delay is 5.390 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Sev_Seg_Led_Data_n\[4\]~reg0 1 REG LCFF_X10_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X10_Y13_N1; Fanout = 1; REG Node = 'Sev_Seg_Led_Data_n\[4\]~reg0'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(3.286 ns) 5.390 ns Sev_Seg_Led_Data_n\[4\] 2 PIN PIN_208 0 " "Info: 2: + IC(2.104 ns) + CELL(3.286 ns) = 5.390 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'Sev_Seg_Led_Data_n\[4\]'" { } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 Sev_Seg_Led_Data_n[4] } "NODE_NAME" } } { "Segment1.v" "" { Text "F:/FPGA4U/Example/FPGA4U/Segment1/Segment1/Segment1.v" 33 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 60.96 % ) " "Info: Total cell delay = 3.286 ns ( 60.96 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.104 ns ( 39.04 % ) " "Info: Total interconnect delay = 2.104 ns ( 39.04 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 Sev_Seg_Led_Data_n[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 {} Sev_Seg_Led_Data_n[4] {} } { 0.000ns 2.104ns } { 0.000ns 3.286ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.850 ns" { Clk Clk~clkctrl Sev_Seg_Led_Data_n[4]~reg0 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.850 ns" { Clk {} Clk~combout {} Clk~clkctrl {} Sev_Seg_Led_Data_n[4]~reg0 {} } { 0.000ns 0.000ns 0.139ns 0.905ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 Sev_Seg_Led_Data_n[4] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.390 ns" { Sev_Seg_Led_Data_n[4]~reg0 {} Sev_Seg_Led_Data_n[4] {} } { 0.000ns 2.104ns } { 0.000ns 3.286ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
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