reg24bit.hif

自己使用VHDL语言编写的24位寄存器.主要用于DDS中

HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	lpm_ff.tdf
	{
		lpm_ff [DEVICE_FAMILY,LPM_FFTYPE=DFF,LPM_SVALUE=0,LPM_AVALUE=0,LPM_WIDTH,USE_LPM_FOR_AHDL_OPERATORS] [lpm_constant.inc,aglobal.inc]
		{
			1 [DEVICE_FAMILY=MAX7000S,LPM_FFTYPE=DFF,LPM_SVALUE=0,LPM_AVALUE=0,LPM_WIDTH=24,USE_LPM_FOR_AHDL_OPERATORS=OFF] [Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10,Q11,Q12,Q13,Q14,Q15,Q16,Q17,Q18,Q19,Q20,Q21,Q22,Q23,ACLR,Enable,CLOCK,DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,DATA8,DATA9,DATA10,DATA11,DATA12,DATA13,DATA14,DATA15,DATA16,DATA17,DATA18,DATA19,DATA20,DATA21,DATA22,DATA23];
		}
	}
	reg24bit.vhd
	{
		reg24bit [] [U1546459.DLS,U3031072.DLS,U2043679.DLS,U7449008.DLS,U1147235.DLS]
		{
			0 [] [];
		}
	}
}
TREE
{
	reg24bit::(0,0):(0): reg24bit.vhd
	{
		lpm_ff:1:(14,12):(53,r): lpm_ff.tdf;
	}
}