ds_fh.tan.qmsg

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "P26 register MSC51:inst9\|latch_out2\[4\] register DS_code:inst14\|mux_code:inst16\|DS_code 78.31 MHz 12.77 ns Internal " "Info: Clock \"P26\" has Internal fmax of 78.31 MHz between source register \"MSC51:inst9\|latch_out2\[4\]\" and destination register \"DS_code:inst14\|mux_code:inst16\|DS_code\" (period= 12.77 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.384 ns + Longest register register " "Info: + Longest register to register delay is 5.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns MSC51:inst9\|latch_out2\[4\] 1 REG LCFF_X22_Y3_N31 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y3_N31; Fanout = 6; REG Node = 'MSC51:inst9\|latch_out2\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { MSC51:inst9|latch_out2[4] } "NODE_NAME" } } { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.178 ns) 1.070 ns DS_code:inst15\|mux_code:inst16\|Mux0~372 2 COMB LCCOMB_X22_Y3_N6 10 " "Info: 2: + IC(0.892 ns) + CELL(0.178 ns) = 1.070 ns; Loc. = LCCOMB_X22_Y3_N6; Fanout = 10; COMB Node = 'DS_code:inst15\|mux_code:inst16\|Mux0~372'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.070 ns" { MSC51:inst9|latch_out2[4] DS_code:inst15|mux_code:inst16|Mux0~372 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.574 ns) + CELL(0.322 ns) 1.966 ns DS_code:inst14\|mux_code:inst16\|Mux0~309 3 COMB LCCOMB_X22_Y3_N10 1 " "Info: 3: + IC(0.574 ns) + CELL(0.322 ns) = 1.966 ns; Loc. = LCCOMB_X22_Y3_N10; Fanout = 1; COMB Node = 'DS_code:inst14\|mux_code:inst16\|Mux0~309'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { DS_code:inst15|mux_code:inst16|Mux0~372 DS_code:inst14|mux_code:inst16|Mux0~309 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.296 ns) + CELL(0.178 ns) 2.440 ns DS_code:inst14\|mux_code:inst16\|Mux0~310 4 COMB LCCOMB_X22_Y3_N18 2 " "Info: 4: + IC(0.296 ns) + CELL(0.178 ns) = 2.440 ns; Loc. = LCCOMB_X22_Y3_N18; Fanout = 2; COMB Node = 'DS_code:inst14\|mux_code:inst16\|Mux0~310'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.474 ns" { DS_code:inst14|mux_code:inst16|Mux0~309 DS_code:inst14|mux_code:inst16|Mux0~310 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.178 ns) 2.915 ns DS_code:inst14\|mux_code:inst16\|Mux0~311 5 COMB LCCOMB_X22_Y3_N24 1 " "Info: 5: + IC(0.297 ns) + CELL(0.178 ns) = 2.915 ns; Loc. = LCCOMB_X22_Y3_N24; Fanout = 1; COMB Node = 'DS_code:inst14\|mux_code:inst16\|Mux0~311'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.475 ns" { DS_code:inst14|mux_code:inst16|Mux0~310 DS_code:inst14|mux_code:inst16|Mux0~311 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.319 ns) 3.531 ns DS_code:inst14\|mux_code:inst16\|Mux0~312 6 COMB LCCOMB_X22_Y3_N16 1 " "Info: 6: + IC(0.297 ns) + CELL(0.319 ns) = 3.531 ns; Loc. = LCCOMB_X22_Y3_N16; Fanout = 1; COMB Node = 'DS_code:inst14\|mux_code:inst16\|Mux0~312'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.616 ns" { DS_code:inst14|mux_code:inst16|Mux0~311 DS_code:inst14|mux_code:inst16|Mux0~312 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.322 ns) 4.152 ns DS_code:inst14\|mux_code:inst16\|Mux0~316 7 COMB LCCOMB_X22_Y3_N14 1 " "Info: 7: + IC(0.299 ns) + CELL(0.322 ns) = 4.152 ns; Loc. = LCCOMB_X22_Y3_N14; Fanout = 1; COMB Node = 'DS_code:inst14\|mux_code:inst16\|Mux0~316'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { DS_code:inst14|mux_code:inst16|Mux0~312 DS_code:inst14|mux_code:inst16|Mux0~316 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.319 ns) 4.768 ns DS_code:inst14\|mux_code:inst16\|Mux0~319 8 COMB LCCOMB_X22_Y3_N8 1 " "Info: 8: + IC(0.297 ns) + CELL(0.319 ns) = 4.768 ns; Loc. = LCCOMB_X22_Y3_N8; Fanout = 1; COMB Node = 'DS_code:inst14\|mux_code:inst16\|Mux0~319'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.616 ns" { DS_code:inst14|mux_code:inst16|Mux0~316 DS_code:inst14|mux_code:inst16|Mux0~319 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.319 ns) 5.384 ns DS_code:inst14\|mux_code:inst16\|DS_code 9 REG LCCOMB_X22_Y3_N2 1 " "Info: 9: + IC(0.297 ns) + CELL(0.319 ns) = 5.384 ns; Loc. = LCCOMB_X22_Y3_N2; Fanout = 1; REG Node = 'DS_code:inst14\|mux_code:inst16\|DS_code'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.616 ns" { DS_code:inst14|mux_code:inst16|Mux0~319 DS_code:inst14|mux_code:inst16|DS_code } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.135 ns ( 39.65 % ) " "Info: Total cell delay = 2.135 ns ( 39.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.249 ns ( 60.35 % ) " "Info: Total interconnect delay = 3.249 ns ( 60.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.384 ns" { MSC51:inst9|latch_out2[4] DS_code:inst15|mux_code:inst16|Mux0~372 DS_code:inst14|mux_code:inst16|Mux0~309 DS_code:inst14|mux_code:inst16|Mux0~310 DS_code:inst14|mux_code:inst16|Mux0~311 DS_code:inst14|mux_code:inst16|Mux0~312 DS_code:inst14|mux_code:inst16|Mux0~316 DS_code:inst14|mux_code:inst16|Mux0~319 DS_code:inst14|mux_code:inst16|DS_code } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.384 ns" { MSC51:inst9|latch_out2[4] DS_code:inst15|mux_code:inst16|Mux0~372 DS_code:inst14|mux_code:inst16|Mux0~309 DS_code:inst14|mux_code:inst16|Mux0~310 DS_code:inst14|mux_code:inst16|Mux0~311 DS_code:inst14|mux_code:inst16|Mux0~312 DS_code:inst14|mux_code:inst16|Mux0~316 DS_code:inst14|mux_code:inst16|Mux0~319 DS_code:inst14|mux_code:inst16|DS_code } { 0.000ns 0.892ns 0.574ns 0.296ns 0.297ns 0.297ns 0.299ns 0.297ns 0.297ns } { 0.000ns 0.178ns 0.322ns 0.178ns 0.178ns 0.319ns 0.322ns 0.319ns 0.319ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "1.375 ns - Smallest " "Info: - Smallest clock skew is 1.375 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "P26 destination 5.830 ns + Shortest register " "Info: + Shortest clock path from clock \"P26\" to destination register is 5.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.933 ns) 0.933 ns P26 1 CLK PIN_61 3 " "Info: 1: + IC(0.000 ns) + CELL(0.933 ns) = 0.933 ns; Loc. = PIN_61; Fanout = 3; CLK Node = 'P26'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { P26 } "NODE_NAME" } } { "DS_FH.bdf" "" { Schematic "E:/Quartus/DS_FH/DS_FH.bdf" { { 528 -352 -184 544 "P26" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.085 ns) + CELL(0.319 ns) 3.337 ns MSC51:inst9\|wr_enable2 2 REG LCCOMB_X21_Y3_N0 6 " "Info: 2: + IC(2.085 ns) + CELL(0.319 ns) = 3.337 ns; Loc. = LCCOMB_X21_Y3_N0; Fanout = 6; REG Node = 'MSC51:inst9\|wr_enable2'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.404 ns" { P26 MSC51:inst9|wr_enable2 } "NODE_NAME" } } { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.296 ns) + CELL(0.879 ns) 4.512 ns MSC51:inst9\|latch_out2\[1\] 3 REG LCFF_X21_Y3_N15 3 " "Info: 3: + IC(0.296 ns) + CELL(0.879 ns) = 4.512 ns; Loc. = LCFF_X21_Y3_N15; Fanout = 3; REG Node = 'MSC51:inst9\|latch_out2\[1\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.175 ns" { MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[1] } "NODE_NAME" } } { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.358 ns) 4.870 ns DS_code:inst14\|mux_code:inst16\|Mux1~186 4 COMB LCCOMB_X21_Y3_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.358 ns) = 4.870 ns; Loc. = LCCOMB_X21_Y3_N14; Fanout = 2; COMB Node = 'DS_code:inst14\|mux_code:inst16\|Mux1~186'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.358 ns" { MSC51:inst9|latch_out2[1] DS_code:inst14|mux_code:inst16|Mux1~186 } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.178 ns) 5.830 ns DS_code:inst14\|mux_code:inst16\|DS_code 5 REG LCCOMB_X22_Y3_N2 1 " "Info: 5: + IC(0.782 ns) + CELL(0.178 ns) = 5.830 ns; Loc. = LCCOMB_X22_Y3_N2; Fanout = 1; REG Node = 'DS_code:inst14\|mux_code:inst16\|DS_code'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.960 ns" { DS_code:inst14|mux_code:inst16|Mux1~186 DS_code:inst14|mux_code:inst16|DS_code } "NODE_NAME" } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.667 ns ( 45.75 % ) " "Info: Total cell delay = 2.667 ns ( 45.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.163 ns ( 54.25 % ) " "Info: Total interconnect delay = 3.163 ns ( 54.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.830 ns" { P26 MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[1] DS_code:inst14|mux_code:inst16|Mux1~186 DS_code:inst14|mux_code:inst16|DS_code } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.830 ns" { P26 P26~combout MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[1] DS_code:inst14|mux_code:inst16|Mux1~186 DS_code:inst14|mux_code:inst16|DS_code } { 0.000ns 0.000ns 2.085ns 0.296ns 0.000ns 0.782ns } { 0.000ns 0.933ns 0.319ns 0.879ns 0.358ns 0.178ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "P26 source 4.455 ns - Longest register " "Info: - Longest clock path from clock \"P26\" to source register is 4.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.933 ns) 0.933 ns P26 1 CLK PIN_61 3 " "Info: 1: + IC(0.000 ns) + CELL(0.933 ns) = 0.933 ns; Loc. = PIN_61; Fanout = 3; CLK Node = 'P26'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { P26 } "NODE_NAME" } } { "DS_FH.bdf" "" { Schematic "E:/Quartus/DS_FH/DS_FH.bdf" { { 528 -352 -184 544 "P26" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.085 ns) + CELL(0.319 ns) 3.337 ns MSC51:inst9\|wr_enable2 2 REG LCCOMB_X21_Y3_N0 6 " "Info: 2: + IC(2.085 ns) + CELL(0.319 ns) = 3.337 ns; Loc. = LCCOMB_X21_Y3_N0; Fanout = 6; REG Node = 'MSC51:inst9\|wr_enable2'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.404 ns" { P26 MSC51:inst9|wr_enable2 } "NODE_NAME" } } { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.516 ns) + CELL(0.602 ns) 4.455 ns MSC51:inst9\|latch_out2\[4\] 3 REG LCFF_X22_Y3_N31 6 " "Info: 3: + IC(0.516 ns) + CELL(0.602 ns) = 4.455 ns; Loc. = LCFF_X22_Y3_N31; Fanout = 6; REG Node = 'MSC51:inst9\|latch_out2\[4\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[4] } "NODE_NAME" } } { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.854 ns ( 41.62 % ) " "Info: Total cell delay = 1.854 ns ( 41.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.601 ns ( 58.38 % ) " "Info: Total interconnect delay = 2.601 ns ( 58.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.455 ns" { P26 MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.455 ns" { P26 P26~combout MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[4] } { 0.000ns 0.000ns 2.085ns 0.516ns } { 0.000ns 0.933ns 0.319ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.830 ns" { P26 MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[1] DS_code:inst14|mux_code:inst16|Mux1~186 DS_code:inst14|mux_code:inst16|DS_code } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.830 ns" { P26 P26~combout MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[1] DS_code:inst14|mux_code:inst16|Mux1~186 DS_code:inst14|mux_code:inst16|DS_code } { 0.000ns 0.000ns 2.085ns 0.296ns 0.000ns 0.782ns } { 0.000ns 0.933ns 0.319ns 0.879ns 0.358ns 0.178ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.455 ns" { P26 MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.455 ns" { P26 P26~combout MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[4] } { 0.000ns 0.000ns 2.085ns 0.516ns } { 0.000ns 0.933ns 0.319ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.099 ns + " "Info: + Micro setup delay of destination is 2.099 ns" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } } { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 9 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.384 ns" { MSC51:inst9|latch_out2[4] DS_code:inst15|mux_code:inst16|Mux0~372 DS_code:inst14|mux_code:inst16|Mux0~309 DS_code:inst14|mux_code:inst16|Mux0~310 DS_code:inst14|mux_code:inst16|Mux0~311 DS_code:inst14|mux_code:inst16|Mux0~312 DS_code:inst14|mux_code:inst16|Mux0~316 DS_code:inst14|mux_code:inst16|Mux0~319 DS_code:inst14|mux_code:inst16|DS_code } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.384 ns" { MSC51:inst9|latch_out2[4] DS_code:inst15|mux_code:inst16|Mux0~372 DS_code:inst14|mux_code:inst16|Mux0~309 DS_code:inst14|mux_code:inst16|Mux0~310 DS_code:inst14|mux_code:inst16|Mux0~311 DS_code:inst14|mux_code:inst16|Mux0~312 DS_code:inst14|mux_code:inst16|Mux0~316 DS_code:inst14|mux_code:inst16|Mux0~319 DS_code:inst14|mux_code:inst16|DS_code } { 0.000ns 0.892ns 0.574ns 0.296ns 0.297ns 0.297ns 0.299ns 0.297ns 0.297ns } { 0.000ns 0.178ns 0.322ns 0.178ns 0.178ns 0.319ns 0.322ns 0.319ns 0.319ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.830 ns" { P26 MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[1] DS_code:inst14|mux_code:inst16|Mux1~186 DS_code:inst14|mux_code:inst16|DS_code } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.830 ns" { P26 P26~combout MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[1] DS_code:inst14|mux_code:inst16|Mux1~186 DS_code:inst14|mux_code:inst16|DS_code } { 0.000ns 0.000ns 2.085ns 0.296ns 0.000ns 0.782ns } { 0.000ns 0.933ns 0.319ns 0.879ns 0.358ns 0.178ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.455 ns" { P26 MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[4] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.455 ns" { P26 P26~combout MSC51:inst9|wr_enable2 MSC51:inst9|latch_out2[4] } { 0.000ns 0.000ns 2.085ns 0.516ns } { 0.000ns 0.933ns 0.319ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "sys_reset register register ddscontrol:inst17\|current_state\[3\] ddscontrol:inst17\|w_clk 380.08 MHz Internal " "Info: Clock \"sys_reset\" Internal fmax is restricted to 380.08 MHz between source register \"ddscontrol:inst17\|current_state\[3\]\" and destination register \"ddscontrol:inst17\|w_clk\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.455 ns + Longest register register " "Info: + Longest register to register delay is 1.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ddscontrol:inst17\|current_state\[3\] 1 REG LCFF_X7_Y10_N27 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y10_N27; Fanout = 21; REG Node = 'ddscontrol:inst17\|current_state\[3\]'" {  } { { "d:/altera/70/quartus/bin/Timin