ds_fh.tan.qmsg

来自「扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DS_FH -c DS_FH --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DS_FH -c DS_FH --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "DS_code:inst14\|mux_code:inst16\|DS_code " "Warning: Node \"DS_code:inst14\|mux_code:inst16\|DS_code\" is a latch" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MSC51:inst9\|wr_enable2 " "Warning: Node \"MSC51:inst9\|wr_enable2\" is a latch" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "convolutional_encoder:inst3\|control " "Warning: Node \"convolutional_encoder:inst3\|control\" is a latch" {  } { { "convolutional_encoder.vhd" "" { Text "E:/Quartus/DS_FH/convolutional_encoder.vhd" 11 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MSC51:inst9\|wr_enable3 " "Warning: Node \"MSC51:inst9\|wr_enable3\" is a latch" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "DS_code:inst15\|mux_code:inst16\|DS_code " "Warning: Node \"DS_code:inst15\|mux_code:inst16\|DS_code\" is a latch" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 9 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "MSC51:inst9\|wr_enable1 " "Warning: Node \"MSC51:inst9\|wr_enable1\" is a latch" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}