ds_fh.tan.qmsg

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sys_clk " "Info: Assuming node \"sys_clk\" is an undefined clock" {  } { { "DS_FH.bdf" "" { Schematic "E:/Quartus/DS_FH/DS_FH.bdf" { { 88 -240 -72 104 "sys_clk" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "sys_clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "P26 " "Info: Assuming node \"P26\" is an undefined clock" {  } { { "DS_FH.bdf" "" { Schematic "E:/Quartus/DS_FH/DS_FH.bdf" { { 528 -352 -184 544 "P26" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "P26" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "sys_reset " "Info: Assuming node \"sys_reset\" is an undefined clock" {  } { { "DS_FH.bdf" "" { Schematic "E:/Quartus/DS_FH/DS_FH.bdf" { { 104 -240 -72 120 "sys_reset" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "sys_reset" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ALE " "Info: Assuming node \"ALE\" is an undefined clock" {  } { { "DS_FH.bdf" "" { Schematic "E:/Quartus/DS_FH/DS_FH.bdf" { { 544 -352 -184 560 "ALE" "" } } } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "ALE" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "13 " "Warning: Found 13 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|wr_enable1 " "Info: Detected ripple clock \"MSC51:inst9\|wr_enable1\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|wr_enable1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|wr_enable3 " "Info: Detected ripple clock \"MSC51:inst9\|wr_enable3\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|wr_enable3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|wr_enable2 " "Info: Detected ripple clock \"MSC51:inst9\|wr_enable2\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 19 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|wr_enable2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst11\|clkx4 " "Info: Detected ripple clock \"clk_div:inst11\|clkx4\" as buffer" {  } { { "clk_div.vhd" "" { Text "E:/Quartus/DS_FH/clk_div.vhd" 10 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst11\|clkx4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst11\|reset_DDS " "Info: Detected ripple clock \"clk_div:inst11\|reset_DDS\" as buffer" {  } { { "clk_div.vhd" "" { Text "E:/Quartus/DS_FH/clk_div.vhd" 11 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst11\|reset_DDS" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|latch_out2\[5\] " "Info: Detected ripple clock \"MSC51:inst9\|latch_out2\[5\]\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|latch_out2\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|latch_out2\[4\] " "Info: Detected ripple clock \"MSC51:inst9\|latch_out2\[4\]\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|latch_out2\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|latch_out2\[3\] " "Info: Detected ripple clock \"MSC51:inst9\|latch_out2\[3\]\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|latch_out2\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst11\|clk " "Info: Detected ripple clock \"clk_div:inst11\|clk\" as buffer" {  } { { "clk_div.vhd" "" { Text "E:/Quartus/DS_FH/clk_div.vhd" 11 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst11\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "DS_code:inst14\|mux_code:inst16\|Mux1~185 " "Info: Detected gated clock \"DS_code:inst14\|mux_code:inst16\|Mux1~185\" as buffer" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "DS_code:inst14\|mux_code:inst16\|Mux1~185" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|latch_out2\[2\] " "Info: Detected ripple clock \"MSC51:inst9\|latch_out2\[2\]\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|latch_out2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "MSC51:inst9\|latch_out2\[1\] " "Info: Detected ripple clock \"MSC51:inst9\|latch_out2\[1\]\" as buffer" {  } { { "MSC51.vhd" "" { Text "E:/Quartus/DS_FH/MSC51.vhd" 63 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "MSC51:inst9\|latch_out2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "DS_code:inst14\|mux_code:inst16\|Mux1~186 " "Info: Detected gated clock \"DS_code:inst14\|mux_code:inst16\|Mux1~186\" as buffer" {  } { { "mux_code.vhd" "" { Text "E:/Quartus/DS_FH/mux_code.vhd" 19 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "DS_code:inst14\|mux_code:inst16\|Mux1~186" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}