ds_fh.map.rpt

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP2C8Q208C7        ;                    ;
; Top-level entity name                                              ; DS_FH              ; DS_FH              ;
; Family name                                                        ; Cyclone II         ; Stratix            ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Safe State Machine                                                 ; Off                ; Off                ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Ignore Verilog initial constructs                                  ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; DSP Block Balancing                                                ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                     ; Off                ; Off                ;
; Optimization Technique -- Cyclone II                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70                 ; 70                 ;
; Auto Carry Chains                                                  ; On                 ; On                 ;
; Auto Open-Drain Pins                                               ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                              ; Off                ; Off                ;
; Perform gate-level register retiming                               ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax             ; On                 ; On                 ;
; Auto ROM Replacement                                               ; On                 ; On                 ;
; Auto RAM Replacement                                               ; On                 ; On                 ;
; Auto Shift Register Replacement                                    ; On                 ; On                 ;
; Auto Clock Enable Replacement                                      ; On                 ; On                 ;
; Allow Synchronous Control Signals                                  ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                             ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                  ; Off                ; Off                ;
; Auto Resource Sharing                                              ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                 ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                      ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                  ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                 ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                    ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report           ; 100                ; 100                ;
; Use smart compilation                                              ; Off                ; Off                ;
+--------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                       ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------+
; DS_FH.bdf                        ; yes             ; User Block Diagram/Schematic File  ; E:/Quartus/DS_FH/DS_FH.bdf                                         ;
; mux_hopset.vhd                   ; yes             ; User VHDL File                     ; E:/Quartus/DS_FH/mux_hopset.vhd                                    ;
; mux_framer.vhd                   ; yes             ; User VHDL File                     ; E:/Quartus/DS_FH/mux_framer.vhd                                    ;
; clk_div.vhd                      ; yes             ; User VHDL File                     ; E:/Quartus/DS_FH/clk_div.vhd                                       ;
; piso8.vhd                        ; yes             ; User VHDL File                     ; E:/Quartus/DS_FH/piso8.vhd                                         ;
; ddscontrol.vhd                   ; yes             ; Other                              ; E:/Quartus/DS_FH/ddscontrol.vhd                                    ;
; initialization.vhd               ; yes             ; Other                              ; E:/Quartus/DS_FH/initialization.vhd                                ;
; hopset_generator.vhd             ; yes             ; Other                              ; E:/Quartus/DS_FH/hopset_generator.vhd                              ;
; QPSK.bdf                         ; yes             ; Other                              ; E:/Quartus/DS_FH/QPSK.bdf                                          ;
; add.vhd                          ; yes             ; Other                              ; E:/Quartus/DS_FH/add.vhd                                           ;
; tiaozhi.vhd                      ; yes             ; Other                              ; E:/Quartus/DS_FH/tiaozhi.vhd                                       ;
; sin_rom.vhd                      ; yes             ; Other                              ; E:/Quartus/DS_FH/sin_rom.vhd                                       ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; d:/altera/70/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; d:/altera/70/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; d:/altera/70/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; d:/altera/70/quartus/libraries/megafunctions/lpm_decode.inc        ;
; aglobal70.inc                    ; yes             ; Megafunction                       ; d:/altera/70/quartus/libraries/megafunctions/aglobal70.inc         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; d:/altera/70/quartus/libraries/megafunctions/a_rdenreg.inc         ;