ds_fh.map.rpt
来自「扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现」· RPT 代码 · 共 401 行 · 第 1/5 页
RPT
401 行
; |altsyncram:altsyncram_component| ; 63 (0) ; 37 (0) ; 2560 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component ;
; |altsyncram_sc91:auto_generated| ; 63 (0) ; 37 (0) ; 2560 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated ;
; |altsyncram_mk82:altsyncram1| ; 0 (0) ; 0 (0) ; 2560 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|altsyncram_mk82:altsyncram1 ;
; |sld_mod_ram_rom:mgl_prim2| ; 63 (38) ; 37 (28) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|sld_mod_ram_rom:mgl_prim2 ;
; |sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr| ; 25 (25) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr ;
; |tiaozhi:inst14| ; 20 (20) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|QPSK:inst1|tiaozhi:inst14 ;
; |clk_div:inst11| ; 28 (28) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|clk_div:inst11 ;
; |convolutional_encoder:inst3| ; 11 (11) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|convolutional_encoder:inst3 ;
; |ddscontrol:inst17| ; 99 (99) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|ddscontrol:inst17 ;
; |differential_encoder:inst5| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|differential_encoder:inst5 ;
; |framer:inst4| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|framer:inst4 ;
; |hopset_generator:inst2| ; 2 (2) ; 31 (31) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|hopset_generator:inst2 ;
; |indata:inst10| ; 9 (9) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|indata:inst10 ;
; |initialization:inst| ; 19 (19) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|initialization:inst ;
; |mux_hopset:inst7| ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|mux_hopset:inst7 ;
; |muxdata:inst19| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|muxdata:inst19 ;
; |lpm_mux:lpm_mux_component| ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|muxdata:inst19|lpm_mux:lpm_mux_component ;
; |mux_03e:auto_generated| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|muxdata:inst19|lpm_mux:lpm_mux_component|mux_03e:auto_generated ;
; |piso8:inst18| ; 12 (12) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |DS_FH|piso8:inst18 ;
+------------------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+----------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+----------------+
; QPSK:inst1|sin_rom:inst1|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|altsyncram_mk82:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 10 ; 256 ; 10 ; 2560 ; sin_ROM256.mif ;
; QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|altsyncram_mk82:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 256 ; 10 ; 256 ; 10 ; 2560 ; sin_ROM256.mif ;
+--------------------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+------+----------------+
+-------------------------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+-------------------------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+-------------------------------------+------------------------+
; DS_code:inst14|mux_code:inst16|DS_code ; DS_code:inst14|mux_code:inst16|Mux1 ; yes ;
; DS_code:inst15|mux_code:inst16|DS_code ; DS_code:inst14|mux_code:inst16|Mux1 ; yes ;
; convolutional_encoder:inst3|control ; GND ; yes ;
; MSC51:inst9|wr_enable2 ; P26 ; yes ;
; MSC51:inst9|wr_enable3 ; P26 ; yes ;
; MSC51:inst9|wr_enable1 ; P26 ; yes ;
; Number of user-specified and inferred latches = 6 ; ; ;
+----------------------------------------------------+-------------------------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+-----------------------------------------+------------------------------------------+
; Register name ; Reason for Removal ;
+-----------------------------------------+------------------------------------------+
; inst14/inst13/inst1/count[0] ; Merged with inst15/inst13/inst1/count[0] ;
; inst14/inst13/inst1/enable ; Merged with inst15/inst13/inst1/enable ;
; inst14/inst13/inst1/count[1] ; Merged with inst15/inst13/inst1/count[1] ;
; inst14/inst13/inst1/count[2] ; Merged with inst15/inst13/inst1/count[2] ;
; inst14/inst13/inst1/count[3] ; Merged with inst15/inst13/inst1/count[3] ;
; inst14/inst13/inst1/count[4] ; Merged with inst15/inst13/inst1/count[4] ;
; inst14/inst13/inst1/count[5] ; Merged with inst15/inst13/inst1/count[5] ;
; inst14/inst13/inst1/count[6] ; Merged with inst15/inst13/inst1/count[6] ;
; inst14/inst13/inst1/count[7] ; Merged with inst15/inst13/inst1/count[7] ;
; inst14/inst13/inst1/count[8] ; Merged with inst15/inst13/inst1/count[8] ;
; inst14/inst13/inst1/count[9] ; Merged with inst15/inst13/inst1/count[9] ;
; inst14/inst13/inst/count[0] ; Merged with inst15/inst13/inst/count[0] ;
; inst14/inst13/inst/enable ; Merged with inst15/inst13/inst/enable ;
; inst14/inst13/inst/count[1] ; Merged with inst15/inst13/inst/count[1] ;
; inst14/inst13/inst/count[2] ; Merged with inst15/inst13/inst/count[2] ;
; inst14/inst13/inst/count[3] ; Merged with inst15/inst13/inst/count[3] ;
; inst14/inst13/inst/count[4] ; Merged with inst15/inst13/inst/count[4] ;
; inst14/inst13/inst/count[5] ; Merged with inst15/inst13/inst/count[5] ;
; inst14/inst13/inst/count[6] ; Merged with inst15/inst13/inst/count[6] ;
; inst14/inst13/inst/count[7] ; Merged with inst15/inst13/inst/count[7] ;
; inst14/inst13/inst/count[8] ; Merged with inst15/inst13/inst/count[8] ;
; inst14/inst13/inst/count[9] ; Merged with inst15/inst13/inst/count[9] ;
; inst14/i⌨️ 快捷键说明
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