ds_fh.map.rpt

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

Analysis & Synthesis report for DS_FH
Sun Jan 13 08:51:27 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. User-Specified and Inferred Latches
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Inverted Register Statistics
 12. Multiplexer Restructuring Statistics (Restructuring Performed)
 13. Source assignments for QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|altsyncram_mk82:altsyncram1
 14. Source assignments for QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 15. Source assignments for QPSK:inst1|sin_rom:inst1|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|altsyncram_mk82:altsyncram1
 16. Source assignments for QPSK:inst1|sin_rom:inst1|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr
 17. Source assignments for sld_hub:sld_hub_inst
 18. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 19. Parameter Settings for User Entity Instance: QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component
 20. Parameter Settings for User Entity Instance: QPSK:inst1|sin_rom:inst|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|sld_mod_ram_rom:mgl_prim2
 21. Parameter Settings for User Entity Instance: QPSK:inst1|sin_rom:inst1|altsyncram:altsyncram_component
 22. Parameter Settings for User Entity Instance: QPSK:inst1|sin_rom:inst1|altsyncram:altsyncram_component|altsyncram_sc91:auto_generated|sld_mod_ram_rom:mgl_prim2
 23. Parameter Settings for User Entity Instance: muxdata:inst19|LPM_MUX:lpm_mux_component
 24. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 25. In-System Memory Content Editor Settings
 26. Analysis & Synthesis Resource Utilization by Entity
 27. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Jan 13 08:51:26 2008   ;
; Quartus II Version                 ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                      ; DS_FH                                   ;
; Top-level Entity Name              ; DS_FH                                   ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 616                                     ;
;     Total combinational functions  ; 616                                     ;
;     Dedicated logic registers      ; 595                                     ;
; Total registers                    ; N/A until Partition Merge               ;
; Total pins                         ; N/A until Partition Merge               ;
; Total virtual pins                 ; N/A until Partition Merge               ;
; Total memory bits                  ; N/A until Partition Merge               ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge               ;
; Total PLLs                         ; N/A until Partition Merge               ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;