myled.tan.qmsg

利用if语句实现流水灯设计。工具：Quartus ii 6.0 语言：VHDL

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 2 -1 0 } } { "f:/quartus/win/Assignment Editor.qase" "" { Assignment "f:/quartus/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:\\a1:a\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] register b\[2\] 103.09 MHz 9.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 103.09 MHz between source register \"lpm_counter:\\a1:a\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]\" and destination register \"b\[2\]\" (period= 9.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.300 ns + Longest register register " "Info: + Longest register to register delay is 8.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:\\a1:a\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 1 REG LC8_I20 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_I20; Fanout = 3; REG Node = 'lpm_counter:\\a1:a\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.500 ns) 2.800 ns LessThan0~83 2 COMB LC8_I22 1 " "Info: 2: + IC(1.300 ns) + CELL(1.500 ns) = 2.800 ns; Loc. = LC8_I22; Fanout = 1; COMB Node = 'LessThan0~83'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "2.800 ns" { lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] LessThan0~83 } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 4.400 ns LessThan0~84 3 COMB LC7_I22 15 " "Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.400 ns; Loc. = LC7_I22; Fanout = 15; COMB Node = 'LessThan0~84'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.600 ns" { LessThan0~83 LessThan0~84 } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.400 ns) 7.200 ns b\[2\]~20 4 COMB LC6_I19 3 " "Info: 4: + IC(1.400 ns) + CELL(1.400 ns) = 7.200 ns; Loc. = LC6_I19; Fanout = 3; COMB Node = 'b\[2\]~20'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "2.800 ns" { LessThan0~84 b[2]~20 } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.900 ns) 8.300 ns b\[2\] 5 REG LC4_I19 9 " "Info: 5: + IC(0.200 ns) + CELL(0.900 ns) = 8.300 ns; Loc. = LC4_I19; Fanout = 9; REG Node = 'b\[2\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.100 ns" { b[2]~20 b[2] } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 62.65 % ) " "Info: Total cell delay = 5.200 ns ( 62.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 37.35 % ) " "Info: Total interconnect delay = 3.100 ns ( 37.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "8.300 ns" { lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] LessThan0~83 LessThan0~84 b[2]~20 b[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "8.300 ns" { lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] LessThan0~83 LessThan0~84 b[2]~20 b[2] } { 0.000ns 1.300ns 0.200ns 1.400ns 0.200ns } { 0.000ns 1.500ns 1.400ns 1.400ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 17 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns b\[2\] 2 REG LC4_I19 9 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC4_I19; Fanout = 9; REG Node = 'b\[2\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk b[2] } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk b[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out b[2] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 17 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns lpm_counter:\\a1:a\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\] 2 REG LC8_I20 3 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC8_I20; Fanout = 3; REG Node = 'lpm_counter:\\a1:a\[0\]_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[5\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk b[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out b[2] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "f:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "8.300 ns" { lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] LessThan0~83 LessThan0~84 b[2]~20 b[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "8.300 ns" { lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] LessThan0~83 LessThan0~84 b[2]~20 b[2] } { 0.000ns 1.300ns 0.200ns 1.400ns 0.200ns } { 0.000ns 1.500ns 1.400ns 1.400ns 0.900ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk b[2] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out b[2] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y\[7\] b\[0\] 13.400 ns register " "Info: tco from clock \"clk\" to destination pin \"y\[7\]\" through register \"b\[0\]\" is 13.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns clk 1 CLK PIN_79 17 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns b\[0\] 2 REG LC3_I19 11 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_I19; Fanout = 11; REG Node = 'b\[0\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "1.300 ns" { clk b[0] } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns ( 62.86 % ) " "Info: Total cell delay = 2.200 ns ( 62.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 37.14 % ) " "Info: Total interconnect delay = 1.300 ns ( 37.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk b[0] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out b[0] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.200 ns + Longest register pin " "Info: + Longest register to pin delay is 9.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b\[0\] 1 REG LC3_I19 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_I19; Fanout = 11; REG Node = 'b\[0\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "" { b[0] } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.500 ns) 3.400 ns comb~234 2 COMB LC1_I14 1 " "Info: 2: + IC(1.900 ns) + CELL(1.500 ns) = 3.400 ns; Loc. = LC1_I14; Fanout = 1; COMB Node = 'comb~234'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.400 ns" { b[0] comb~234 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(4.900 ns) 9.200 ns y\[7\] 3 PIN PIN_88 0 " "Info: 3: + IC(0.900 ns) + CELL(4.900 ns) = 9.200 ns; Loc. = PIN_88; Fanout = 0; PIN Node = 'y\[7\]'" {  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "5.800 ns" { comb~234 y[7] } "NODE_NAME" } } { "myled.vhd" "" { Text "H:/EDA作业/myled/myled.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns ( 69.57 % ) " "Info: Total cell delay = 6.400 ns ( 69.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 30.43 % ) " "Info: Total interconnect delay = 2.800 ns ( 30.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "9.200 ns" { b[0] comb~234 y[7] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "9.200 ns" { b[0] comb~234 y[7] } { 0.000ns 1.900ns 0.900ns } { 0.000ns 1.500ns 4.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "3.500 ns" { clk b[0] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "3.500 ns" { clk clk~out b[0] } { 0.000ns 0.000ns 1.300ns } { 0.000ns 2.200ns 0.000ns } } } { "f:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "f:/quartus/win/TimingClosureFloorplan.fld" "" "9.200 ns" { b[0] comb~234 y[7] } "NODE_NAME" } } { "f:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/quartus/win/Technology_Viewer.qrui" "9.200 ns" { b[0] comb~234 y[7] } { 0.000ns 1.900ns 0.900ns } { 0.000ns 1.500ns 4.900ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 24 18:06:20 2009 " "Info: Processing ended: Tue Mar 24 18:06:20 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}