myled.map.rpt

利用if语句实现流水灯设计。工具：Quartus ii 6.0 语言：VHDL

; Maximum fan-out                   ; 15      ;
; Total fan-out                     ; 88      ;
; Average fan-out                   ; 2.51    ;
+-----------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                              ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                              ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------+
; |myled                                 ; 26 (14)     ; 15           ; 0           ; 9    ; 11 (11)      ; 0 (0)             ; 15 (3)           ; 12 (0)          ; 0 (0)      ; |myled                                                           ;
;    |lpm_counter:\a1:a[0]_rtl_0|        ; 12 (0)      ; 12           ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 12 (0)           ; 12 (0)          ; 0 (0)      ; |myled|lpm_counter:\a1:a[0]_rtl_0                                ;
;       |alt_counter_f10ke:wysi_counter| ; 12 (12)     ; 12           ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 12 (12)          ; 12 (12)         ; 0 (0)      ; |myled|lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; y[0]$latch                                         ; GND                 ; yes                    ;
; y[1]$latch                                         ; GND                 ; yes                    ;
; y[2]$latch                                         ; GND                 ; yes                    ;
; y[3]$latch                                         ; GND                 ; yes                    ;
; y[4]$latch                                         ; GND                 ; yes                    ;
; y[5]$latch                                         ; GND                 ; yes                    ;
; y[6]$latch                                         ; GND                 ; yes                    ;
; y[7]$latch                                         ; GND                 ; yes                    ;
; Number of user-specified and inferred latches = 8  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 15    ;
; Number of registers using Synchronous Clear  ; 12    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------+
; Source assignments for Top-level Entity: |myled ;
+----------------+-------+------+-----------------+
; Assignment     ; Value ; From ; To              ;
+----------------+-------+------+-----------------+
; POWER_UP_LEVEL ; Low   ; -    ; b[0]            ;
; POWER_UP_LEVEL ; Low   ; -    ; b[1]            ;
; POWER_UP_LEVEL ; Low   ; -    ; b[2]            ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[0]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[1]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[2]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[3]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[4]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[5]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[6]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[7]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[8]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[9]         ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[10]        ;
; POWER_UP_LEVEL ; Low   ; -    ; a1:a[11]        ;
+----------------+-------+------+-----------------+


+-----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:\a1:a[0]_rtl_0 ;
+------------------------+-------------------+--------------------------------+
; Parameter Name         ; Value             ; Type                           ;
+------------------------+-------------------+--------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                     ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                   ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                   ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                 ;
; LPM_WIDTH              ; 12                ; Untyped                        ;
; LPM_DIRECTION          ; UP                ; Untyped                        ;
; LPM_MODULUS            ; 0                 ; Untyped                        ;
; LPM_AVALUE             ; UNUSED            ; Untyped                        ;
; LPM_SVALUE             ; UNUSED            ; Untyped                        ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                        ;
; DEVICE_FAMILY          ; ACEX1K            ; Untyped                        ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                        ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH             ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK             ;
; CARRY_CNT_EN           ; SMART             ; Untyped                        ;
; LABWIDE_SCLR           ; ON                ; Untyped                        ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                        ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                        ;
+------------------------+-------------------+--------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Apr 12 16:26:00 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myled -c myled
Info: Found 2 design units, including 1 entities, in source file myled.vhd
    Info: Found design unit 1: myled-bhv
    Info: Found entity 1: myled
Info: Elaborating entity "myled" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at myled.vhd(24): inferring latch(es) for signal or variable "y", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[0]"
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[1]"
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[2]"
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[3]"
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[4]"
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[5]"
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[6]"
Info (10041): Verilog HDL or VHDL info at myled.vhd(24): inferred latch for "y[7]"
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=12) from the following logic: "\a1:a[0]~0"
Info: Found 1 design units, including 1 entities, in source file ../../quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "lpm_counter:\a1:a[0]_rtl_0"
Info: Found 1 design units, including 1 entities, in source file ../../quartus/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "lpm_counter:\a1:a[0]_rtl_0"
Info: Instantiated megafunction "lpm_counter:\a1:a[0]_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "12"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Implemented 35 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 8 output pins
    Info: Implemented 26 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Apr 12 16:26:01 2009
    Info: Elapsed time: 00:00:02