myled.tan.rpt

利用if语句实现流水灯设计。工具：Quartus ii 6.0 语言：VHDL

; N/A   ; None         ; 11.700 ns  ; b[2] ; y[2] ; clk        ;
; N/A   ; None         ; 11.700 ns  ; b[0] ; y[2] ; clk        ;
; N/A   ; None         ; 11.700 ns  ; b[2] ; y[1] ; clk        ;
; N/A   ; None         ; 11.700 ns  ; b[1] ; y[1] ; clk        ;
; N/A   ; None         ; 11.700 ns  ; b[0] ; y[0] ; clk        ;
; N/A   ; None         ; 11.700 ns  ; b[1] ; y[0] ; clk        ;
; N/A   ; None         ; 11.600 ns  ; b[1] ; y[2] ; clk        ;
; N/A   ; None         ; 11.600 ns  ; b[0] ; y[1] ; clk        ;
; N/A   ; None         ; 11.600 ns  ; b[2] ; y[0] ; clk        ;
+-------+--------------+------------+------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Mar 24 18:06:19 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off myled -c myled
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 103.09 MHz between source register "lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]" and destination register "b[2]" (period= 9.7 ns)
    Info: + Longest register to register delay is 8.300 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_I20; Fanout = 3; REG Node = 'lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
        Info: 2: + IC(1.300 ns) + CELL(1.500 ns) = 2.800 ns; Loc. = LC8_I22; Fanout = 1; COMB Node = 'LessThan0~83'
        Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.400 ns; Loc. = LC7_I22; Fanout = 15; COMB Node = 'LessThan0~84'
        Info: 4: + IC(1.400 ns) + CELL(1.400 ns) = 7.200 ns; Loc. = LC6_I19; Fanout = 3; COMB Node = 'b[2]~20'
        Info: 5: + IC(0.200 ns) + CELL(0.900 ns) = 8.300 ns; Loc. = LC4_I19; Fanout = 9; REG Node = 'b[2]'
        Info: Total cell delay = 5.200 ns ( 62.65 % )
        Info: Total interconnect delay = 3.100 ns ( 37.35 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC4_I19; Fanout = 9; REG Node = 'b[2]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
        Info: - Longest clock path from clock "clk" to source register is 3.500 ns
            Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'
            Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC8_I20; Fanout = 3; REG Node = 'lpm_counter:\a1:a[0]_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
            Info: Total cell delay = 2.200 ns ( 62.86 % )
            Info: Total interconnect delay = 1.300 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Micro setup delay of destination is 0.700 ns
Info: tco from clock "clk" to destination pin "y[7]" through register "b[0]" is 13.400 ns
    Info: + Longest clock path from clock "clk" to source register is 3.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_79; Fanout = 17; CLK Node = 'clk'
        Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_I19; Fanout = 11; REG Node = 'b[0]'
        Info: Total cell delay = 2.200 ns ( 62.86 % )
        Info: Total interconnect delay = 1.300 ns ( 37.14 % )
    Info: + Micro clock to output delay of source is 0.700 ns
    Info: + Longest register to pin delay is 9.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_I19; Fanout = 11; REG Node = 'b[0]'
        Info: 2: + IC(1.900 ns) + CELL(1.500 ns) = 3.400 ns; Loc. = LC1_I14; Fanout = 1; COMB Node = 'comb~234'
        Info: 3: + IC(0.900 ns) + CELL(4.900 ns) = 9.200 ns; Loc. = PIN_88; Fanout = 0; PIN Node = 'y[7]'
        Info: Total cell delay = 6.400 ns ( 69.57 % )
        Info: Total interconnect delay = 2.800 ns ( 30.43 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Mar 24 18:06:20 2009
    Info: Elapsed time: 00:00:02