myf_adder.fnsim.qmsg

用例化语句和case语句编写的全加器的VHDL描述。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 14 19:38:47 2009 " "Info: Processing started: Sat Mar 14 19:38:47 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off myf_adder -c myf_adder --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myf_adder -c myf_adder --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "myf_adder.vhd 6 3 " "Info: Found 6 design units, including 3 entities, in source file myf_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 myf_adder-bhv " "Info: Found design unit 1: myf_adder-bhv" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 myh_adder-fh1 " "Info: Found design unit 2: myh_adder-fh1" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 myor2a-one " "Info: Found design unit 3: myor2a-one" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 55 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 myf_adder " "Info: Found entity 1: myf_adder" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 myh_adder " "Info: Found entity 2: myh_adder" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 25 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 myor2a " "Info: Found entity 3: myor2a" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 51 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "myf_adder " "Info: Elaborating entity \"myf_adder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myh_adder myh_adder:u1 " "Info: Elaborating entity \"myh_adder\" for hierarchy \"myh_adder:u1\"" {  } { { "myf_adder.vhd" "u1" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 18 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "co myf_adder.vhd(31) " "Warning (10631): VHDL Process Statement warning at myf_adder.vhd(31): inferring latch(es) for signal or variable \"co\", which holds its previous value in one or more paths through the process" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 31 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "so myf_adder.vhd(31) " "Warning (10631): VHDL Process Statement warning at myf_adder.vhd(31): inferring latch(es) for signal or variable \"so\", which holds its previous value in one or more paths through the process" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 31 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "so myf_adder.vhd(31) " "Info (10041): Verilog HDL or VHDL info at myf_adder.vhd(31): inferred latch for \"so\"" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "co myf_adder.vhd(31) " "Info (10041): Verilog HDL or VHDL info at myf_adder.vhd(31): inferred latch for \"co\"" {  } { { "myf_adder.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 31 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "myor2a myor2a:u3 " "Info: Elaborating entity \"myor2a\" for hierarchy \"myor2a:u3\"" {  } { { "myf_adder.vhd" "u3" { Text "C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd" 20 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 2 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 14 19:38:48 2009 " "Info: Processing ended: Sat Mar 14 19:38:48 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}