myf_adder.map.rpt

用例化语句和case语句编写的全加器的VHDL描述。

; Retiming Meta-Stability Register Sequence Length                   ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                      ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+
; myf_adder.vhd                    ; yes             ; User VHDL File  ; C:/Documents and Settings/Administrator/桌面/myf_adder/myf_adder.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 2     ;
;     -- Combinational with no register       ; 2     ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 0     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 0     ;
;     -- 3 input functions                    ; 2     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 2     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 5     ;
; Maximum fan-out node                        ; cin   ;
; Maximum fan-out                             ; 2     ;
; Total fan-out                               ; 8     ;
; Average fan-out                             ; 1.14  ;
+---------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                               ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name     ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; |myf_adder                 ; 2 (0)       ; 0            ; 0           ; 0    ; 5    ; 0            ; 2 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |myf_adder              ;
;    |myh_adder:u2|          ; 1 (1)       ; 0            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |myf_adder|myh_adder:u2 ;
;    |myor2a:u3|             ; 1 (1)       ; 0            ; 0           ; 0    ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |myf_adder|myor2a:u3    ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sat Mar 14 19:34:43 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off myf_adder -c myf_adder
Info: Found 6 design units, including 3 entities, in source file myf_adder.vhd
    Info: Found design unit 1: myf_adder-bhv
    Info: Found design unit 2: myh_adder-fh1
    Info: Found design unit 3: myor2a-one
    Info: Found entity 1: myf_adder
    Info: Found entity 2: myh_adder
    Info: Found entity 3: myor2a
Info: Elaborating entity "myf_adder" for the top level hierarchy
Info: Elaborating entity "myh_adder" for hierarchy "myh_adder:u1"
Warning (10631): VHDL Process Statement warning at myf_adder.vhd(31): inferring latch(es) for signal or variable "co", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at myf_adder.vhd(31): inferring latch(es) for signal or variable "so", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at myf_adder.vhd(31): inferred latch for "so"
Info (10041): Verilog HDL or VHDL info at myf_adder.vhd(31): inferred latch for "co"
Info: Elaborating entity "myor2a" for hierarchy "myor2a:u3"
Info: Implemented 7 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 2 output pins
    Info: Implemented 2 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Mar 14 19:34:44 2009
    Info: Elapsed time: 00:00:02