sub.mfd

来自「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」· MFD 代码 · 共 1,209 行 · 第 1/5 页

MFD
1,209 行
字号
12345
	# !a<0> & b<0> & !a<1> & !a<2> & b<2>
	# !a<0> & b<0> & b<1> & a<2> & !b<2>
	# !a<0> & b<0> & b<1> & !a<2> & b<2>
	# a<1> & a<2> & !b<2> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB1_7
	# a<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !b<1> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<1> & !a<2> & b<2> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<0> & b<0> & a<1> & !b<1> & !c<3>_BUFR
;Imported pterms FB1_6
	# !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & a<1> & !b<1> & c<3>_BUFR
	# !a<0> & b<0> & !a<1> & b<1>
	# !a<1> & b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB1_9
	# !a<1> & b<1> & c<3>_BUFR
	# a<2> & b<2> & c<3>_BUFR
	# a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<2> & !b<2> & c<3>_BUFR
	# !a<1> & !b<1> & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB1_10
	# !b<0> & a<1> & !b<1> & c<3>_BUFR
	# a<0> & !b<0> & a<1> & b<1> & !c<3>_BUFR
	# a<0> & !b<0> & !a<1> & !b<1> & !c<3>_BUFR
	# !a<1> & b<1> & a<2> & !b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<1> & b<1> & !a<2> & b<2> & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 7 | 15 | c_6_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 8 | a<0>  | b<0>  | b<1>  | c<3>_BUFR  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | a<1>  | EXP36_.EXP  | EXP37_.EXP
INPUTMC | 4 | 0 | 2 | 0 | 4 | 7 | 14 | 7 | 16
INPUTP | 4 | 77 | 66 | 64 | 74
IMPORTS | 2 | 7 | 14 | 7 | 16
EQ | 59 | 
   c<6> = a<0> & b<0> & a<1> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<0> & b<0> & !b<1> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & !b<0> & a<1> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & !b<0> & !b<1> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !b<0> & a<1> & !b<1> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
;Imported pterms FB8_15
	# a<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# a<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_14
	# !a<0> & b<0> & a<1> & b<1> & !c<3>_BUFR & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_17
	# a<0> & !b<0> & a<1> & b<1> & c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_18
	# a<0> & !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 5 | 1 | c_7_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 10 | a<0>  | a<2>  | b<2>  | c<3>_BUFR  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<0>  | EXP32_.EXP  | EXP33_.EXP
INPUTMC | 6 | 0 | 2 | 7 | 17 | 7 | 0 | 2 | 17 | 5 | 0 | 5 | 2
INPUTP | 4 | 77 | 72 | 63 | 66
IMPORTS | 2 | 5 | 0 | 5 | 2
EQ | 61 | 
   c<7> = a<0> & !b<0> & b<2> & !c<3>_BUFR & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !b<2> & !c<3>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & a<2> & !b<2> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<2> & b<2> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_1
	# a<0> & !b<0> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# c<3>_BUFR & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & b<2> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & !b<2> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_18
	# !a<0> & b<0> & !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_3
	# a<2> & !b<2> & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<2> & b<2> & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_4
	# a<0> & !b<0> & a<2> & !b<2> & !c<3>_BUFR & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & b<2> & !c<3>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D;

MACROCELL | 3 | 11 | en_0_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   en<0> = Gnd;

MACROCELL | 3 | 10 | en_7_OBUF
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   en<7> = Vcc;

MACROCELL | 3 | 8 | en_7_OBUF$BUF0
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   en<6> = Vcc;

MACROCELL | 3 | 1 | en_7_OBUF$BUF1
ATTRIBUTES | 264962 | 0
OUTPUTMC | 1 | 3 | 0
INPUTS | 13 | a<0>  | b<0>  | c<3>_BUFR  | c<4>_BUFR  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | a<1>  | b<1>  | a<3>  | b<3>  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | en_7_OBUF$BUF5.EXP
INPUTMC | 7 | 0 | 2 | 1 | 15 | 7 | 17 | 7 | 0 | 0 | 4 | 0 | 13 | 3 | 2
INPUTP | 6 | 77 | 66 | 74 | 64 | 69 | 62
EXPORTS | 1 | 3 | 0
IMPORTS | 1 | 3 | 2
EQ | 15 | 
   en<5> = ;Imported pterms FB4_3
	  Vcc;
    en_7_OBUF$BUF1.EXP  =  a<0> & !b<0> & !c<3>_BUFR & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & !c<3>_BUFR & c<4>_BUFR & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# b<0> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<1> & !b<1> & a<3> & b<3> & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<3> & !b<3> & c<4>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2

MACROCELL | 5 | 11 | en_7_OBUF$BUF2
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   en<4> = Vcc;

MACROCELL | 5 | 14 | en_7_OBUF$BUF3
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   en<3> = Vcc;

MACROCELL | 5 | 16 | en_7_OBUF$BUF4
ATTRIBUTES | 264962 | 0
INPUTS | 0
EQ | 1 | 
   en<2> = Vcc;
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sub.mfd - 源码说明

本页面展示了「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」中的 sub.mfd 源码文件，采用 MFD 编程语言编写，共 1,209 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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