sub.mfd

来自「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」· MFD 代码 · 共 1,209 行 · 第 1/5 页
MFD
1,209 行
	# !a<0> & !b<0> & a<1> & b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & !a<1> & !b<1> & a<2> & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !b<0> & !a<1> & !b<1> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 3 | 16 | EXP30_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 17
INPUTS | 8 | a<1>  | b<1>  | a<3>  | b<3>  | c<4>_BUFR  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
INPUTMC | 4 | 1 | 15 | 0 | 4 | 7 | 0 | 0 | 13
INPUTP | 4 | 74 | 64 | 69 | 62
EXPORTS | 1 | 3 | 17
EQ | 5 | 
       EXP30_.EXP  =  a<1> & !b<1> & !a<3> & !b<3> & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<3> & b<3> & c<4>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2

MACROCELL | 3 | 17 | EXP31_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 0
INPUTS | 10 | a<0>  | c<3>_BUFR  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | a<3>  | b<3>  | c<4>_BUFR  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | EXP30_.EXP
INPUTMC | 7 | 0 | 2 | 7 | 17 | 7 | 0 | 0 | 4 | 1 | 15 | 0 | 13 | 3 | 16
INPUTP | 3 | 77 | 69 | 62
EXPORTS | 1 | 3 | 0
IMPORTS | 1 | 3 | 16
EQ | 19 | 
       EXP31_.EXP  =  !a<0> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<3> & b<3> & c<4>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<3> & !b<3> & c<3>_BUFR & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<3> & !b<3> & c<4>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !a<3> & !b<3> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & !Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
;Imported pterms FB4_17
	# a<1> & !b<1> & !a<3> & !b<3> & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<3> & b<3> & c<4>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2

MACROCELL | 5 | 0 | EXP32_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 1
INPUTS | 9 | a<0>  | b<0>  | c<3>_BUFR  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | c<4>_BUFR  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | a<2>  | b<2>  | EXP34_.EXP
INPUTMC | 5 | 0 | 2 | 7 | 17 | 1 | 15 | 2 | 17 | 5 | 17
INPUTP | 4 | 77 | 66 | 72 | 63
EXPORTS | 1 | 5 | 1
IMPORTS | 1 | 5 | 17
EQ | 19 | 
       EXP32_.EXP  =  a<0> & !b<0> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# c<3>_BUFR & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & a<2> & b<2> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & !b<2> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_18
	# !a<0> & b<0> & !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 5 | 2 | EXP33_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 1
INPUTS | 9 | a<2>  | b<2>  | c<4>_BUFR  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | a<0>  | b<0>  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400  | _10_.EXP
INPUTMC | 5 | 1 | 15 | 7 | 17 | 2 | 17 | 7 | 0 | 5 | 3
INPUTP | 4 | 72 | 63 | 77 | 66
EXPORTS | 1 | 5 | 1
IMPORTS | 1 | 5 | 3
EQ | 22 | 
       EXP33_.EXP  =  a<2> & !b<2> & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<2> & b<2> & c<4>_BUFR & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D
	# !a<0> & b<0> & a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & a<2> & !b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & !a<2> & b<2> & 
	Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB6_4
	# a<0> & !b<0> & a<2> & !b<2> & !c<3>_BUFR & 
	!$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<2> & b<2> & !c<3>_BUFR & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 5 | 17 | EXP34_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 5 | 0
INPUTS | 7 | a<0>  | b<0>  | a<2>  | b<2>  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | $OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400
INPUTMC | 3 | 7 | 17 | 2 | 17 | 7 | 0
INPUTP | 4 | 77 | 66 | 72 | 63
EXPORTS | 1 | 5 | 0
EQ | 7 | 
       EXP34_.EXP  =  !a<0> & b<0> & !a<2> & !b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<2> & b<2> & 
	!Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D & 
	$OpTx$Msub_c_tmp__n0016<0>/Msub_c_tmp__n0016<0>_D2_INV$400 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 7 | 13 | EXP35_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 14
INPUTS | 8 | a<0>  | b<0>  | a<1>  | b<1>  | c<3>_BUFR  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
INPUTMC | 4 | 0 | 2 | 0 | 13 | 2 | 17 | 0 | 4
INPUTP | 4 | 77 | 66 | 74 | 64
EXPORTS | 1 | 7 | 14
EQ | 12 | 
       EXP35_.EXP  =  !a<0> & b<0> & a<1> & b<1> & !c<3>_BUFR & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 7 | 14 | EXP36_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 15
INPUTS | 9 | a<0>  | a<1>  | b<1>  | c<3>_BUFR  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | b<0>  | EXP35_.EXP
INPUTMC | 5 | 0 | 2 | 0 | 4 | 0 | 13 | 2 | 17 | 7 | 13
INPUTP | 4 | 77 | 74 | 64 | 66
EXPORTS | 1 | 7 | 15
IMPORTS | 1 | 7 | 13
EQ | 25 | 
       EXP36_.EXP  =  a<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# a<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & !b<1> & c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2
	# !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_14
	# !a<0> & b<0> & a<1> & b<1> & !c<3>_BUFR & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & b<1> & c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

MACROCELL | 7 | 16 | EXP37_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 7 | 15
INPUTS | 9 | a<0>  | b<0>  | a<1>  | b<1>  | c<3>_BUFR  | Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D  | Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D  | Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2  | Msub_c_tmp_Mxor_Result<1>__n0002<0>/Msub_c_tmp_Mxor_Result<1>__n0002<0>_D.EXP
INPUTMC | 5 | 0 | 2 | 0 | 4 | 2 | 17 | 0 | 13 | 7 | 17
INPUTP | 4 | 77 | 66 | 74 | 64
EXPORTS | 1 | 7 | 15
IMPORTS | 1 | 7 | 17
EQ | 22 | 
       EXP37_.EXP  =  a<0> & !b<0> & a<1> & b<1> & c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# a<0> & !b<0> & a<1> & !b<1> & !c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & !b<1> & c<3>_BUFR & 
	!Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp_Mxor_Result<2>__n0002<0>/Msub_c_tmp_Mxor_Result<2>__n0002<0>_D & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB8_18
	# a<0> & !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# a<0> & !b<0> & !a<1> & b<1> & !c<3>_BUFR & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D
	# !a<0> & b<0> & !a<1> & !b<1> & !c<3>_BUFR & 
	!Msub_c_tmp__n00023/Msub_c_tmp__n00023_D2 & 
	!Msub_c_tmp_Mxor_Result<3>__n0002<0>/Msub_c_tmp_Mxor_Result<3>__n0002<0>_D

PIN | a<0> | 64 | 0 | N/A | 77 | 34 | 3 | 0 | 0 | 15 | 0 | 2 | 1 | 15 | 0 | 7 | 7 | 15 | 5 | 1 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 6 | 0 | 9 | 0 | 11 | 0 | 13 | 0 | 14 | 0 | 16 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 3 | 1 | 3 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 5 | 17 | 7 | 13 | 7 | 14 | 7 | 16 | 7 | 17
PIN | b<0> | 64 | 0 | N/A | 66 | 33 | 3 | 0 | 0 | 15 | 0 | 2 | 1 | 15 | 0 | 7 | 7 | 15 | 5 | 1 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 6 | 0 | 9 | 0 | 11 | 0 | 13 | 0 | 14 | 0 | 16 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 3 | 1 | 5 | 0 | 5 | 2 | 5 | 3 | 5 | 17 | 7 | 13 | 7 | 14 | 7 | 16 | 7 | 17
PIN | a<1> | 64 | 0 | N/A | 74 | 29 | 1 | 17 | 0 | 15 | 0 | 2 | 1 | 15 | 0 | 7 | 7 | 15 | 7 | 17 | 7 | 0 | 0 | 13 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 6 | 0 | 8 | 0 | 9 | 0 | 11 | 0 | 12 | 0 | 14 | 0 | 16 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 3 | 1 | 3 | 16 | 7 | 13 | 7 | 14 | 7 | 16
PIN | b<1> | 64 | 0 | N/A | 64 | 28 | 1 | 17 | 0 | 15 | 0 | 2 | 1 | 15 | 0 | 7 | 7 | 15 | 7 | 17 | 7 | 0 | 0 | 13 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 6 | 0 | 8 | 0 | 9 | 0 | 12 | 0 | 14 | 0 | 16 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 3 | 1 | 3 | 16 | 7 | 13 | 7 | 14 | 7 | 16
PIN | a<2> | 64 | 0 | N/A | 72 | 26 | 0 | 15 | 0 | 2 | 1 | 15 | 0 | 7 | 5 | 1 | 0 | 4 | 0 | 13 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 6 | 0 | 8 | 0 | 9 | 0 | 12 | 0 | 14 | 0 | 16 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 5 | 17
PIN | b<2> | 64 | 0 | N/A | 63 | 27 | 0 | 15 | 0 | 2 | 1 | 15 | 0 | 7 | 5 | 1 | 0 | 4 | 0 | 12 | 0 | 0 | 0 | 1 | 0 | 3 | 0 | 5 | 0 | 6 | 0 | 8 | 0 | 9 | 0 | 11 | 0 | 13 | 0 | 14 | 0 | 16 | 0 | 17 | 1 | 13 | 1 | 14 | 1 | 16 | 1 | 17 | 5 | 0 | 5 | 2 | 5 | 3 | 5 | 17
PIN | a<3> | 64 | 0 | N/A | 69 | 5 | 3 | 0 | 2 | 17 | 3 | 1 | 3 | 16 | 3 | 17
PIN | b<3> | 64 | 0 | N/A | 62 | 5 | 3 | 0 | 2 | 17 | 3 | 1 | 3 | 16 | 3 | 17
PIN | c<1> | 536871040 | 0 | N/A | 133
PIN | c<2> | 536871040 | 0 | N/A | 130
PIN | c<3> | 536871040 | 0 | N/A | 129
PIN | c<4> | 536871040 | 0 | N/A | 127
PIN | c<5> | 536871040 | 0 | N/A | 124
PIN | c<6> | 536871040 | 0 | N/A | 119
PIN | c<7> | 536871040 | 0 | N/A | 118
PIN | en<0> | 536871040 | 0 | N/A | 149
PIN | en<7> | 536871040 | 0 | N/A | 147
PIN | en<6> | 536871040 | 0 | N/A | 146
PIN | en<5> | 536871040 | 0 | N/A | 141
PIN | en<4> | 536871040 | 0 | N/A | 135
PIN | en<3> | 536871040 | 0 | N/A | 139
PIN | en<2> | 536871040 | 0 | N/A | 140
PIN | en<1> | 536871040 | 0 | N/A | 148
PIN | c<0> | 536871040 | 0 | N/A | 134
sub.mfd - 源码说明

本页面展示了「Mars-XC2S50-S-Core-V2.0开发板核心板的说明和设计文档」中的 sub.mfd 源码文件，采用 MFD 编程语言编写，共 1,209 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。
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