shixusuccessful.vhd

用VHDL语言实现TDMA编码,简单

library ieee;
use ieee.std_logic_1164.all;
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entity shixusuccessful is
port(B:in std_logic;
     S3,S2,S1,S0:out std_logic);
end entity shixusuccessful;
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architecture sx1 of shixuesuccessful is