mux.v.bak

多周期处理器--verilog写的,欢迎大家来下载

//Implementation of MUX
module mux2 #	(parameter WIDTH = 8)
(
	input		[WIDTH-1:0]	data0, data1, 
	input		src, 
	output	reg [WIDTH-1:0]	y
);

assign y = src ? data1 : data0;

endmodule