mux3.v.bak

多周期处理器--verilog写的,欢迎大家来下载

module mux3 #	(parameter WIDTH = 8)
(
	input		[WIDTH-1:0]	data0, data1, data2,
	input		src, 
	output	reg [WIDTH-1:0]	y
);
always @(*)
case(src)
    2'b00:y <= data0;
    2'b01:y <= data1;
    2'b10:y <= data2;
endcase
endmodule