datamem.v.bak

多周期处理器--verilog写的,欢迎大家来下载

module DataMem (input clk, we,
   input [31:0] a, wd,
   output [31:0] rd
   );

reg [31:0] RAM[63:0];
assign rd = RAM[a[31:2]];  //word aligned
always @ (posedge clk)
   if (we)
      RAM[a[31:2]] <= wd;    //egde triggering use non-blocking assignment
endmodule