_primary.vhd

来自「多周期处理器--verilog写的,欢迎大家来下载」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity signExt is
    port(
        a               : in     vl_logic_vector(15 downto 0);
        signExt         : in     vl_logic;
        y               : out    vl_logic_vector(31 downto 0)
    );
end signExt;