_primary.vhd

来自「多周期处理器--verilog写的,欢迎大家来下载」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity mux4 is
    generic(
        WIDTH           : integer := 8
    );
    port(
        data0           : in     vl_logic_vector;
        data1           : in     vl_logic_vector;
        data2           : in     vl_logic_vector;
        data3           : in     vl_logic_vector;
        src             : in     vl_logic_vector(1 downto 0);
        y               : out    vl_logic_vector
    );
end mux4;