multicycle.mpf

多周期处理器--verilog写的,欢迎大家来下载

; Directive to license manager:
; vhdl          Immediately reserve a VHDL license
; vlog          Immediately reserve a Verilog license
; plus          Immediately reserve a VHDL and Verilog license
; nomgc         Do not look for Mentor Graphics Licenses
; nomti         Do not look for Model Technology Licenses
; noqueue       Do not wait in the license queue when a license isn't available
; License = plus

; Stop the simulator after an assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; Assertion Message Format
; %S - Severity Level 
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"

; Assertion File - alternate file for storing assertion messages
; AssertFile = assert.log

; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic

; VSIM Startup command
; Startup = do startup.do

; File for saving command transcript
TranscriptFile = transcript

; File for saving command history 
;CommandHistory = cmdhist.log

; Specify whether paths in simulator commands should be described 
; in VHDL or Verilog format. For VHDL, PathSeparator = /
; for Verilog, PathSeparator = .
PathSeparator = /

; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :

; Disable assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1

; Default force kind. May be freeze, drive, or deposit 
; or in other terms, fixed, wired or charged.
; DefaultForceKind = freeze

; If zero, open files when elaborated
; else open files on first read or write
; DelayFileOpen = 0

; Control VHDL files opened for write
;   0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0

; Control number of VHDL files open concurrently
;   This number should always be less then the 
;   current ulimit setting for max file descriptors
;   0 = unlimited
ConcurrentFileLimit = 40

; This controls the number of hierarchical regions displayed as
; part of a signal name shown in the waveform window.  The default
; value or a value of zero tells VSIM to display the full name.
; WaveSignalNameWidth = 0

; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1

; Turn off warnings from the IEEE numeric_std and numeric_bit
; packages.
; NumericStdNoWarnings = 1

; Control the format of a generate statement label. Don't quote it.
; GenerateFormat = %s__%d

; Specify whether checkpoint files should be compressed.
; The default is to be compressed.
; CheckpointCompressMode = 0

; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 17
Project_File_0 = F:/Quartus/altera/72/multicycle/Mem.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1229082144 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = F:/Quartus/altera/72/multicycle/Processor.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228990118 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = F:/Quartus/altera/72/multicycle/adder.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1227860386 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = F:/Quartus/altera/72/multicycle/signExt.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228283765 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = F:/Quartus/altera/72/multicycle/top.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228995766 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = F:/Quartus/altera/72/multicycle/Controller.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1229083219 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = F:/Quartus/altera/72/multicycle/mux3.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228992820 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = F:/Quartus/altera/72/multicycle/mux4.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228992864 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = F:/Quartus/altera/72/multicycle/aludec.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1229082898 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = F:/Quartus/altera/72/multicycle/Datapath.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1229089464 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = F:/Quartus/altera/72/multicycle/top_tb.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1229082345 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = F:/Quartus/altera/72/multicycle/maindec.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1229091012 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = F:/Quartus/altera/72/multicycle/SL2.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1227707567 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = F:/Quartus/altera/72/multicycle/mux.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228995545 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = F:/Quartus/altera/72/multicycle/ALU.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1229090178 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = F:/Quartus/altera/72/multicycle/flopr.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228997241 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = F:/Quartus/altera/72/multicycle/RegFile.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1228998262 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick = 
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick = 
PSL_DoubleClick = Edit
PSL_CustomDoubleClick = 
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick = 
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick = 
TCL_DoubleClick = Edit
TCL_CustomDoubleClick = 
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick = 
VCD_DoubleClick = Edit
VCD_CustomDoubleClick = 
SDF_DoubleClick = Edit
SDF_CustomDoubleClick = 
XML_DoubleClick = Edit
XML_CustomDoubleClick = 
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick = 
EditorState = {tabbed horizontal 1} {F:/Quartus/altera/72/multicycle/Controller.v 0 0} {F:/Quartus/altera/72/multicycle/aludec.v 0 0} {F:/Quartus/altera/72/multicycle/Processor.v 0 0} {F:/Quartus/altera/72/multicycle/Mem.v 0 0} {F:/Quartus/altera/72/multicycle/Datapath.v 0 0} {F:/Quartus/altera/72/multicycle/flopr.v 0 0} {F:/Quartus/altera/72/multicycle/ALU.v 0 0} {F:/Quartus/altera/72/multicycle/RegFile.v 0 0} {F:/Quartus/altera/72/multicycle/top_tb.v 0 0} {F:/Quartus/altera/72/multicycle/mux.v 0 0} {F:/Quartus/altera/72/multicycle/top.v 0 0} {F:/Quartus/altera/72/multicycle/mux3.v 0 0} {F:/Quartus/altera/72/multicycle/mux4.v 0 0} {F:/Quartus/altera/72/multicycle/adder.v 0 0} {F:/Quartus/altera/72/multicycle/maindec.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1