m_control.vhd

With shift add way to implement multiply harware circuit.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY M_control IS
	PORT ( clk, start            : IN  STD_LOGIC ;
	       output_lsb, output_msb      : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0):= "11"  ;
	       sr_mode                     : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0):= "00" ;
	       load_lopnd, done            : OUT STD_LOGIC := '1' ;
	       load_result, samp_ena       : OUT STD_LOGIC := '0' );
END M_control ;

ARCHITECTURE SM OF M_control IS
type states is ( idle, init1, init2, mc1, mc2, mc3, mc4, mc5, mc6, mc7, mc8, result1, result2) ;
signal currentS : states := idle ;

BEGIN
p1:	process(clk) 
       begin
       if (clk'EVENT AND clk = '1') then
           case currentS is
              when idle => 
                     if start = '1' then 
                        currentS <= init1 ; 
                        else 
                        currentS <= idle ; 
                     end if ;
                     load_result <= '0' ;
                     samp_ena  <= '0' ;
                     sr_mode <= "00" ;
             when init1 =>
                      samp_ena  <= '1' ;
                      currentS <= init2 ;
                      sr_mode <= "11" ;
            when init2 =>
                      currentS <=  mc1 ;
                      load_result <= '1' ;
                      sr_mode <= "01" ;
              when mc1 =>
                      currentS <= STATES'RIGHTOF(mc1)  ;
              when mc2 =>
                      currentS <= STATES'RIGHTOF(mc2)  ;
              when mc3 =>
                      currentS <= STATES'RIGHTOF(mc3)  ;
              when mc4 =>
                      currentS <= STATES'RIGHTOF(mc4)  ;
              when mc5 =>
                      currentS <= STATES'RIGHTOF(mc5)  ;
              when mc6 =>
                      currentS <= STATES'RIGHTOF(mc6)  ;
              when mc7 =>
                      currentS <= STATES'RIGHTOF(mc7)  ;
              when mc8 =>
                    currentS <= result1  ;                   
                    samp_ena  <= '0' ;
                    sr_mode <= "00" ;
              when result1 =>
                    currentS <= result2  ;
              when result2 =>
                    currentS <= idle   ;
                    load_result <= '0' ;

           end case ;
       end if ;     
      end process  p1 ;
 
 p2:  process(currentS) 
       begin
          case currentS is
              when idle => 
                   load_lopnd  <= '1' ;
                   output_lsb <= "11" ;
                   output_msb <= "11" ;
                   done <= '1'; 
              when init1 =>
                   load_lopnd  <= '0' ;
                   output_lsb <= "11" ;
                   output_msb <= "11" ;
                   done <= '0'; 
              when init2 =>
                   load_lopnd  <= '1' ;
                   output_lsb <= "11" ;
                   output_msb <= "11" ;
                   done <= '0'; 
              when mc1|mc2|mc3|mc4|mc5|mc6|mc7|mc8 =>
                   load_lopnd  <= '1' ;
                   output_lsb <= "11" ;
                   output_msb <= "11" ;
                   done <= '0'; 
              when result1 =>
                   load_lopnd  <= '1' ;
                   output_lsb <= "00" ;
                   output_msb <= "11" ;
                   done <= '0'; 
              when result2 =>
                   load_lopnd  <= '1' ;
                   output_lsb <= "11" ;
                   output_msb <= "00" ;
                   done <= '0'; 
           end case ;
       end process  p2 ;
      
END SM;