📄 j_tribus.vhd
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library ieee ;
use ieee.std_logic_1164.all ;
entity j_tribus is
port( triout1 : in std_logic_vector(7 downto 0) ;
output_lsbn : in std_logic_vector( 1 downto 0) ;
triout2 : in std_logic_vector(7 downto 0) ;
output_msbn : in std_logic_vector( 1 downto 0) ;
tribus : out std_logic_vector( 7 downto 0):="ZZZZZZZZ" );
end j_tribus ;
architecture dataflow of j_tribus is
begin
process (output_lsbn, output_msbn)
begin
if ((output_lsbn = "00") and (output_msbn = "11")) then
tribus <= triout1 ;
elsif ((output_lsbn = "11" ) and (output_msbn = "00")) then
tribus <= triout2 ;
else
tribus <= "ZZZZZZZZ" ;
end if ;
end process ;
end dataflow ;
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