cnt64.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

architecture SCHEMATIC of UCEBITA0_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component LCELL2_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                  F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  MP : In    STD_LOGIC;
                  MS : In    STD_LOGIC;
                  NP : In    STD_LOGIC;
                  NS : In    STD_LOGIC;
                  OP : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  QC : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC;
                  FZ : Out   STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC;
                  QZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   I_1 : LCELL2_CNT64
      Port Map ( A1=>ENH2, A2=>ENL3, A3=>ENH3, A4=>ENL2, A5=>ENH4,
                 A6=>ENL1, B1=>GND, B2=>GND, C1=>QFB, C2=>GND, D1=>VCC,
                 D2=>QFB, E1=>GND, E2=>GND, F1=>VCC, F2=>GND, F3=>VCC,
                 F4=>GND, F5=>VCC, F6=>GND, MP=>GND, MS=>VCC, NP=>GND,
                 NS=>GND, OP=>ENH1, OS=>GND, QC=>clk, QR=>CLR, QS=>GND,
                 AZ=>open, FZ=>open, NZ=>open, OZ=>open, QZ=>Q_DUMMY );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity CNT64_0 is
      Port (     clk : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                 EN1 : In    STD_LOGIC;
                 EN2 : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR (5 downto 0) );
end CNT64_0;


architecture SCHEMATIC of CNT64_0 is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal   Q1Q2Q3 : STD_LOGIC;
   signal   UCTECO : STD_LOGIC;
   signal ENBUFFN2 : STD_LOGIC;
   signal  Q5BUFF1 : STD_LOGIC;
   signal  Q4BUFF1 : STD_LOGIC;
   signal  Q0BUFF1 : STD_LOGIC;
	signal 		GND : STD_LOGIC := '0';
   signal ENBUFFN1 : STD_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
   signal     N_13 : STD_LOGIC;
   signal Q_DUMMY : STD_LOGIC_VECTOR  (5 downto 0);

   component UCEBITA0_CNT64
      Port (     clk : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                ENH1 : In    STD_LOGIC;
                ENH2 : In    STD_LOGIC;
                ENH3 : In    STD_LOGIC;
                ENH4 : In    STD_LOGIC;
                ENL1 : In    STD_LOGIC;
                ENL2 : In    STD_LOGIC;
                ENL3 : In    STD_LOGIC;
                 QFB : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I0_CNT64
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component MUX4X2_CNT64
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                  S0 : In    STD_LOGIC;
                  S1 : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component BUFF_CNT64
      Port (       A : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND3I0_CNT64
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFFP_CNT64
      Port (     clk : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

begin


   Q(5 downto 0) <= Q_DUMMY(5 downto 0);
   I_64 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN1, ENH2=>Q0BUFF1,
                 ENH3=>Q_DUMMY(1), ENH4=>Q_DUMMY(2), ENL1=>GND,
                 ENL2=>GND, ENL3=>GND, QFB=>Q_DUMMY(3), Q=>Q_DUMMY(3) );
   I_66 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN2, ENH2=>Q4BUFF1,
                 ENH3=>VCC, ENH4=>VCC, ENL1=>UCTECO, ENL2=>GND,
                 ENL3=>GND, QFB=>Q5BUFF1, Q=>Q_DUMMY(5) );
   I_67 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN2, ENH2=>VCC,
                 ENH3=>VCC, ENH4=>VCC, ENL1=>UCTECO, ENL2=>GND,
                 ENL3=>GND, QFB=>Q4BUFF1, Q=>Q_DUMMY(4) );
   I_68 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN1, ENH2=>Q0BUFF1,
                 ENH3=>Q_DUMMY(1), ENH4=>VCC, ENL1=>GND, ENL2=>GND,
                 ENL3=>GND, QFB=>Q_DUMMY(2), Q=>Q_DUMMY(2) );
   I_69 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN1, ENH2=>Q0BUFF1,
                 ENH3=>VCC, ENH4=>VCC, ENL1=>GND, ENL2=>GND, ENL3=>GND,
                 QFB=>Q_DUMMY(1), Q=>Q_DUMMY(1) );
   I_70 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN1, ENH2=>VCC,
                 ENH3=>VCC, ENH4=>VCC, ENL1=>GND, ENL2=>GND, ENL3=>GND,
                 QFB=>Q0BUFF1, Q=>Q_DUMMY(0) );
   I_61 : AND2I0_CNT64
      Port Map ( A=>EN1, B=>EN2, Q=>ENBUFFN2 );
   I_62 : AND2I0_CNT64
      Port Map ( A=>EN1, B=>EN2, Q=>ENBUFFN1 );
   I_34 : MUX4X2_CNT64
      Port Map ( A=>VCC, B=>Q_DUMMY(0), C=>VCC, D=>Q_DUMMY(0),
                 S0=>Q1Q2Q3, S1=>ENBUFFN1, Q=>N_13 );
   I_51 : BUFF_CNT64
      Port Map ( A=>Q_DUMMY(4), Q=>Q4BUFF1 );
   I_50 : BUFF_CNT64
      Port Map ( A=>Q_DUMMY(5), Q=>Q5BUFF1 );
   I_49 : BUFF_CNT64
      Port Map ( A=>Q_DUMMY(0), Q=>Q0BUFF1 );
   I_17 : AND3I0_CNT64
      Port Map ( A=>Q_DUMMY(1), B=>Q_DUMMY(2), C=>Q_DUMMY(3), Q=>Q1Q2Q3 );
   I_18 : DFFP_CNT64
      Port Map ( clk=>clk, D=>N_13, PRE=>CLR, Q=>UCTECO );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity UCEBITA1_CNT64 is
      Port (     clk : In    STD_LOGIC;
                ENH1 : In    STD_LOGIC;
                ENH2 : In    STD_LOGIC;
                ENH3 : In    STD_LOGIC;
                ENH4 : In    STD_LOGIC;
                ENL1 : In    STD_LOGIC;
                ENL2 : In    STD_LOGIC;
                ENL3 : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                 QFB : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end UCEBITA1_CNT64;


architecture SCHEMATIC of UCEBITA1_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component LCELL2_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                  F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  MP : In    STD_LOGIC;
                  MS : In    STD_LOGIC;
                  NP : In    STD_LOGIC;
                  NS : In    STD_LOGIC;
                  OP : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  QC : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC;
                  FZ : Out   STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC;
                  QZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   I_1 : LCELL2_CNT64
      Port Map ( A1=>ENH2, A2=>ENL3, A3=>ENH3, A4=>ENL2, A5=>ENH4,
                 A6=>ENL1, B1=>GND, B2=>GND, C1=>QFB, C2=>GND, D1=>VCC,
                 D2=>QFB, E1=>GND, E2=>GND, F1=>VCC, F2=>GND, F3=>VCC,
                 F4=>GND, F5=>VCC, F6=>GND, MP=>GND, MS=>VCC, NP=>GND,
                 NS=>GND, OP=>ENH1, OS=>GND, QC=>clk, QR=>GND, QS=>PRE,
                 AZ=>open, FZ=>open, NZ=>open, OZ=>open, QZ=>Q_DUMMY );

end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity CNT64_1 is
      Port (     clk : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                 EN1 : In    STD_LOGIC;
                 EN2 : In    STD_LOGIC;
                   Q : Out   STD_LOGIC_VECTOR (5 downto 0) );
end CNT64_1;


architecture SCHEMATIC of CNT64_1 is

	attribute syn_macro : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
   signal   Q1Q2Q3 : STD_LOGIC;
   signal   UCTECO : STD_LOGIC;
   signal ENBUFFN2 : STD_LOGIC;
   signal  Q5BUFF1 : STD_LOGIC;
   signal  Q4BUFF1 : STD_LOGIC;
   signal  Q0BUFF1 : STD_LOGIC;
	signal 		GND : STD_LOGIC := '0';
   signal ENBUFFN1 : STD_LOGIC;
	signal 		VCC : STD_LOGIC := '1';
   signal     N_13 : STD_LOGIC;
   signal Q_DUMMY : STD_LOGIC_VECTOR  (5 downto 0);

   component UCEBITA0_CNT64
      Port (     clk : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                ENH1 : In    STD_LOGIC;
                ENH2 : In    STD_LOGIC;
                ENH3 : In    STD_LOGIC;
                ENH4 : In    STD_LOGIC;
                ENL1 : In    STD_LOGIC;
                ENL2 : In    STD_LOGIC;
                ENL3 : In    STD_LOGIC;
                 QFB : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component UCEBITA1_CNT64
      Port (     clk : In    STD_LOGIC;
                ENH1 : In    STD_LOGIC;
                ENH2 : In    STD_LOGIC;
                ENH3 : In    STD_LOGIC;
                ENH4 : In    STD_LOGIC;
                ENL1 : In    STD_LOGIC;
                ENL2 : In    STD_LOGIC;
                ENL3 : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                 QFB : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I0_CNT64
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component MUX4X2_CNT64
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                  S0 : In    STD_LOGIC;
                  S1 : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component BUFF_CNT64
      Port (       A : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND3I0_CNT64
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFFP_CNT64
      Port (     clk : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

begin


   Q(5 downto 0) <= Q_DUMMY(5 downto 0);
   I_64 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN2, ENH2=>VCC,
                 ENH3=>VCC, ENH4=>VCC, ENL1=>UCTECO, ENL2=>GND,
                 ENL3=>GND, QFB=>Q4BUFF1, Q=>Q_DUMMY(4) );
   I_65 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN2, ENH2=>Q4BUFF1,
                 ENH3=>VCC, ENH4=>VCC, ENL1=>UCTECO, ENL2=>GND,
                 ENL3=>GND, QFB=>Q5BUFF1, Q=>Q_DUMMY(5) );
   I_68 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN1, ENH2=>Q0BUFF1,
                 ENH3=>Q_DUMMY(1), ENH4=>Q_DUMMY(2), ENL1=>GND,
                 ENL2=>GND, ENL3=>GND, QFB=>Q_DUMMY(3), Q=>Q_DUMMY(3) );
   I_69 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN1, ENH2=>Q0BUFF1,
                 ENH3=>Q_DUMMY(1), ENH4=>VCC, ENL1=>GND, ENL2=>GND,
                 ENL3=>GND, QFB=>Q_DUMMY(2), Q=>Q_DUMMY(2) );
   I_70 : UCEBITA0_CNT64
      Port Map ( clk=>clk, CLR=>CLR, ENH1=>ENBUFFN1, ENH2=>Q0BUFF1,
                 ENH3=>VCC, ENH4=>VCC, ENL1=>GND, ENL2=>GND, ENL3=>GND,
                 QFB=>Q_DUMMY(1), Q=>Q_DUMMY(1) );
   I_63 : UCEBITA1_CNT64
      Port Map ( clk=>clk, ENH1=>ENBUFFN1, ENH2=>VCC, ENH3=>VCC,
                 ENH4=>VCC, ENL1=>GND, ENL2=>GND, ENL3=>GND, PRE=>CLR,
                 QFB=>Q0BUFF1, Q=>Q_DUMMY(0) );
   I_61 : AND2I0_CNT64
      Port Map ( A=>EN1, B=>EN2, Q=>ENBUFFN2 );
   I_62 : AND2I0_CNT64
      Port Map ( A=>EN1, B=>EN2, Q=>ENBUFFN1 );
   I_34 : MUX4X2_CNT64
      Port Map ( A=>VCC, B=>Q_DUMMY(0), C=>VCC, D=>Q_DUMMY(0),
                 S0=>Q1Q2Q3, S1=>ENBUFFN1, Q=>N_13 );
   I_51 : BUFF_CNT64
      Port Map ( A=>Q_DUMMY(4), Q=>Q4BUFF1 );
   I_50 : BUFF_CNT64
      Port Map ( A=>Q_DUMMY(5), Q=>Q5BUFF1 );
   I_49 : BUFF_CNT64
      Port Map ( A=>Q_DUMMY(0), Q=>Q0BUFF1 );
   I_17 : AND3I0_CNT64
      Port Map ( A=>Q_DUMMY(1), B=>Q_DUMMY(2), C=>Q_DUMMY(3), Q=>Q1Q2Q3 );
   I_18 : DFFP_CNT64
      Port Map ( clk=>clk, D=>N_13, PRE=>CLR, Q=>UCTECO );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;

entity AND4I1_CNT64 is
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end AND4I1_CNT64;

architecture SCHEMATIC of AND4I1_CNT64 is

	attribute syn_macro : integer;
	attribute ql_gate   : integer;
	attribute syn_macro of SCHEMATIC : architecture is 1;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
	signal 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component FRAG_A_CNT64
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   QL1 : FRAG_A_CNT64
      Port Map ( A1=>A, A2=>GND, A3=>B, A4=>GND, A5=>C, A6=>D,
                 AZ=>Q_DUMMY );

end SCHEMATIC;