📄 cnt64.vhd
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PRE : In STD_LOGIC;
Q : Out STD_LOGIC );
end DFFPC_CNT64;
architecture SCHEMATIC of DFFPC_CNT64 is
attribute syn_macro : integer;
attribute ql_gate : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
signal N_1 : STD_LOGIC;
signal N_2 : STD_LOGIC;
signal VCC : STD_LOGIC := '1';
signal N_3 : STD_LOGIC;
signal GND : STD_LOGIC := '0';
signal Q_DUMMY : STD_LOGIC;
component FRAG_F_CNT64
Port ( F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
FZ : Out STD_LOGIC );
end component;
component FRAG_A_CNT64
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
AZ : Out STD_LOGIC );
end component;
component FRAG_Q_CNT64
Port ( QC : In STD_LOGIC;
QD : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
QZ : Out STD_LOGIC );
end component;
component FRAG_M_CNT64
Port ( B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
NSS : In STD_LOGIC;
OS : In STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC );
end component;
begin
Q <= Q_DUMMY;
I_3 : FRAG_F_CNT64
Port Map ( F1=>VCC, F2=>GND, F3=>VCC, F4=>GND, F5=>VCC, F6=>GND,
FZ=>N_1 );
I_2 : FRAG_A_CNT64
Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
AZ=>N_2 );
I_1 : FRAG_Q_CNT64
Port Map ( QC=>clk, QD=>N_3, QR=>CLR, QS=>PRE, QZ=>Q_DUMMY );
QL1 : FRAG_M_CNT64
Port Map ( B1=>VCC, B2=>GND, C1=>VCC, C2=>GND, D1=>VCC, D2=>GND,
E1=>D, E2=>GND, NSS=>N_1, OS=>N_2, NZ=>open, OZ=>N_3 );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;
entity OR2I1_CNT64 is
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
Q : Out STD_LOGIC );
end OR2I1_CNT64;
architecture SCHEMATIC of OR2I1_CNT64 is
attribute syn_macro : integer;
attribute ql_gate : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
signal N_1 : STD_LOGIC;
signal GND : STD_LOGIC := '0';
signal N_2 : STD_LOGIC;
signal VCC : STD_LOGIC := '1';
signal Q_DUMMY : STD_LOGIC;
component FRAG_F_CNT64
Port ( F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
FZ : Out STD_LOGIC );
end component;
component FRAG_M_CNT64
Port ( B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
NSS : In STD_LOGIC;
OS : In STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC );
end component;
component FRAG_A_CNT64
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
AZ : Out STD_LOGIC );
end component;
begin
Q <= Q_DUMMY;
I_2 : FRAG_F_CNT64
Port Map ( F1=>VCC, F2=>A, F3=>B, F4=>GND, F5=>VCC, F6=>GND,
FZ=>N_1 );
I_1 : FRAG_M_CNT64
Port Map ( B1=>VCC, B2=>GND, C1=>VCC, C2=>GND, D1=>VCC, D2=>GND,
E1=>GND, E2=>VCC, NSS=>N_1, OS=>N_2, NZ=>Q_DUMMY,
OZ=>open );
QL3 : FRAG_A_CNT64
Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
AZ=>N_2 );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;
entity AND3I1_CNT64 is
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
C : In STD_LOGIC;
Q : Out STD_LOGIC );
end AND3I1_CNT64;
architecture SCHEMATIC of AND3I1_CNT64 is
attribute syn_macro : integer;
attribute ql_gate : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
signal VCC : STD_LOGIC := '1';
signal GND : STD_LOGIC := '0';
signal Q_DUMMY : STD_LOGIC;
component FRAG_A_CNT64
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
AZ : Out STD_LOGIC );
end component;
begin
Q <= Q_DUMMY;
QL1 : FRAG_A_CNT64
Port Map ( A1=>A, A2=>GND, A3=>B, A4=>GND, A5=>VCC, A6=>C,
AZ=>Q_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;
entity AND3I0_CNT64 is
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
C : In STD_LOGIC;
Q : Out STD_LOGIC );
end AND3I0_CNT64;
architecture SCHEMATIC of AND3I0_CNT64 is
attribute syn_macro : integer;
attribute ql_gate : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
signal GND : STD_LOGIC := '0';
signal Q_DUMMY : STD_LOGIC;
component FRAG_A_CNT64
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
AZ : Out STD_LOGIC );
end component;
begin
Q <= Q_DUMMY;
QL1 : FRAG_A_CNT64
Port Map ( A1=>A, A2=>GND, A3=>B, A4=>GND, A5=>C, A6=>GND,
AZ=>Q_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;
entity BUFF_CNT64 is
Port ( A : In STD_LOGIC;
Q : Out STD_LOGIC );
end BUFF_CNT64;
architecture SCHEMATIC of BUFF_CNT64 is
attribute syn_macro : integer;
attribute ql_gate : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
signal GND : STD_LOGIC := '0';
signal VCC : STD_LOGIC := '1';
signal Q_DUMMY : STD_LOGIC;
component FRAG_A_CNT64
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
AZ : Out STD_LOGIC );
end component;
begin
Q <= Q_DUMMY;
QL1 : FRAG_A_CNT64
Port Map ( A1=>A, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
AZ=>Q_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;
entity MUX4X2_CNT64 is
Port ( A : In STD_LOGIC;
B : In STD_LOGIC;
C : In STD_LOGIC;
D : In STD_LOGIC;
S0 : In STD_LOGIC;
S1 : In STD_LOGIC;
Q : Out STD_LOGIC );
end MUX4X2_CNT64;
architecture SCHEMATIC of MUX4X2_CNT64 is
attribute syn_macro : integer;
attribute ql_gate : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
signal N_1 : STD_LOGIC;
signal N_2 : STD_LOGIC;
signal VCC : STD_LOGIC := '1';
signal GND : STD_LOGIC := '0';
signal Q_DUMMY : STD_LOGIC;
component FRAG_A_CNT64
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
AZ : Out STD_LOGIC );
end component;
component FRAG_F_CNT64
Port ( F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
FZ : Out STD_LOGIC );
end component;
component FRAG_M_CNT64
Port ( B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
NSS : In STD_LOGIC;
OS : In STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC );
end component;
begin
Q <= Q_DUMMY;
I_2 : FRAG_A_CNT64
Port Map ( A1=>S1, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
AZ=>N_2 );
I_1 : FRAG_F_CNT64
Port Map ( F1=>S0, F2=>GND, F3=>VCC, F4=>GND, F5=>VCC, F6=>GND,
FZ=>N_1 );
QL3 : FRAG_M_CNT64
Port Map ( B1=>A, B2=>GND, C1=>VCC, C2=>B, D1=>C, D2=>GND, E1=>D,
E2=>GND, NSS=>N_1, OS=>N_2, NZ=>open, OZ=>Q_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;
entity LCELL2_CNT64 is
Port ( A1 : In STD_LOGIC;
A2 : In STD_LOGIC;
A3 : In STD_LOGIC;
A4 : In STD_LOGIC;
A5 : In STD_LOGIC;
A6 : In STD_LOGIC;
B1 : In STD_LOGIC;
B2 : In STD_LOGIC;
C1 : In STD_LOGIC;
C2 : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
E1 : In STD_LOGIC;
E2 : In STD_LOGIC;
F1 : In STD_LOGIC;
F2 : In STD_LOGIC;
F3 : In STD_LOGIC;
F4 : In STD_LOGIC;
F5 : In STD_LOGIC;
F6 : In STD_LOGIC;
MP : In STD_LOGIC;
MS : In STD_LOGIC;
NP : In STD_LOGIC;
NS : In STD_LOGIC;
OP : In STD_LOGIC;
OS : In STD_LOGIC;
QC : In STD_LOGIC;
QR : In STD_LOGIC;
QS : In STD_LOGIC;
AZ : Out STD_LOGIC;
FZ : Out STD_LOGIC;
NZ : Out STD_LOGIC;
OZ : Out STD_LOGIC;
QZ : Out STD_LOGIC );
end LCELL2_CNT64;
architecture BEHAVIORAL of LCELL2_CNT64 is
attribute ql_frag : integer;
attribute ql_frag of BEHAVIORAL : architecture is 1;
signal MZ, AZ_DUMMY, FZ_DUMMY : STD_LOGIC;
signal NZ_DUMMY, OZ_DUMMY : STD_LOGIC;
signal TOPMUX_Z, BOTMUX_Z, MIDMUX_Z : STD_LOGIC;
begin
AZ <= AZ_DUMMY;
FZ <= FZ_DUMMY;
NZ <= NZ_DUMMY;
OZ <= OZ_DUMMY;
AZ_DUMMY <= A1 and (not A2) and A3 and (not A4) and A5 and (not A6) after 1000 ps;
TOPMUX_Z <= AZ_DUMMY when OP ='1' else OS;
MZ <= (C1 and not C2) when MIDMUX_Z = '1' else (B1 and not B2);
MIDMUX_Z <= FZ_DUMMY when MP = '1' else MS;
NZ_DUMMY <= (E1 and not E2) when BOTMUX_Z = '1' else (D1 and not D2);
BOTMUX_Z <= FZ_DUMMY when NP = '1' else NS;
FZ_DUMMY <= F1 and (not F2) and F3 and (not F4) and F5 and (not F6) after 1000 ps;
OZ_DUMMY <= NZ_DUMMY when TOPMUX_Z = '1' else MZ;
process (QC, QR, QS)
begin
if QR = '1' then
QZ <= '0';
elsif QS = '1' then
QZ <= '1';
elsif QC = '1' and QC'EVENT then
QZ <= OZ_DUMMY;
end if;
end process;
end BEHAVIORAL;
library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE_CNT64.all;
entity UCEBITA0_CNT64 is
Port ( clk : In STD_LOGIC;
CLR : In STD_LOGIC;
ENH1 : In STD_LOGIC;
ENH2 : In STD_LOGIC;
ENH3 : In STD_LOGIC;
ENH4 : In STD_LOGIC;
ENL1 : In STD_LOGIC;
ENL2 : In STD_LOGIC;
ENL3 : In STD_LOGIC;
QFB : In STD_LOGIC;
Q : Out STD_LOGIC );
end UCEBITA0_CNT64;
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